Showing papers on "Thin-film transistor published in 1991"

Method for forming a thin layer on a semiconductor substrate and apparatus therefor

Abstract: A method and apparatus for manufacturing a semiconductor device having a thin layer of material formed on a semiconductor substrate with a much improved interface between them are disclosed. A silicon substrate is heated up to a temperature around 300° C. in the presence of ozone gas under exposure to UV light. Through this process, organic contaminants that might be present on the surface of the silicon substrate are dissipated by oxidation, and a thin oxide film is formed on the substrate surface on the other. The silicon substrate with the thin oxide film coated thereon is then heated up to temperatures of 200°-700° C. in the presence of HCl gas under illumination to UV light to strip the oxide film off the substrate surface, thereby exposing the cleaned substrate surface. Finally, HCl cleaned surface of the silicon substrate is coated with a thin layer of material such as monocrystalline silicon without exposing the cleaned substrate surface. The method provides a semiconductor with the thin layer of material formed thereon having a well-controlled, well organized interface between them.

Thin-layer field-effect transistors with MIS structure whose insulator and semiconductor are made of organic materials

Abstract: A thin-layer field-effect transistor (TFT) with an MIS structure includes a thin semiconductor layer between a source and a drain. The thin semiconductor layer is in contact with one surface of a thin layer made of insulating material, and in contact by its other surface with a conducting grid. The semiconductor is composed of at least one polyconjugated organic compound with a specific molecular weight. The polyconjugated organic compound or polyconjugated organic compounds contain at least 8 conjugated bonds and have a molecular weight of no greater than approximately 2,000. The thin layer of insulating material is made of an insulating organic polymer having a dielectric constant of at least equal to 5. The transistor is useful as a switching or amplifying element.

Process for preparing a polycrystalline semiconductor thin film transistor

Abstract: A process for preparing a polycrystalline semiconductor thin film transistor wherein a non-singlecrystalline semiconductor formed on a transparent insulating substrate is annealed by laser beams, such process comprising forming a gate insulation layer and a gate electrode on the non-singlecrystalline semiconductor; implanting impurity ions into a source-drain region of the semiconductor wherein the gate electrode is used as a mask, and irradiating laser beams from the rear surface side of the transparent insulating substrate to thereby polycrystallize the non-singlecrystalline semiconductor under the gate electrode or improve the crystallinity of the semiconductor without causing the non-singlecrystalline semiconductor in a completely molten state.

Recrystallization of amorphous silicon films deposited by low‐pressure chemical vapor deposition from Si2H6 gas

Abstract: This paper investigated the recrystallization of low‐pressure chemical vapor deposition amorphous silicon (a‐Si) films deposited using Si2H6 gas at various substrate temperatures. The grain size of recrystallized films formed from Si2H6 is larger than that formed from SiH4. The maximum grain size is obtained at the substrate temperature of 460 °C, where the nucleation rate is minimum due to the maximum structural disorder of the Si network. The structural disorder is increased not only by lowering the substrate temperature but also by increasing the deposition rate. The field effect mobility of thin‐film transistors (TFTs) using the recrystallized films reaches 120 cm2 V−1 s−1, even though the highest temperature during the TFT fabrication process is only 600 °C.

Active matrix structure for liquid crystal display elements wherein each of the gate/data lines includes at least a molybdenum-base alloy layer containing 0.5 to 10 wt. % of chromium

Abstract: In an active matrix structure for liquid crystal display elements which includes pixel electrodes arranged in a matrix form on a glass base plate, thin film transistors having their drains connected to the pixel electrodes, respectively, data lines each connected to sources of the thin film transistors of one column and gate lines connected to gates of the thin film transistors of one row, there are provided in the same plane a light blocking layer disposed opposite each of the thin film transistors across an insulating layer, a storage capacitance electrode disposed partly opposite each of the pixel electrodes across the insulating layer and storage capacitance lines for interconnecting the capacitance electrodes. The light blocking layers, the storage capacitance electrodes and the storage capacitance lines are formed of the same material and at the same time.

Enlargement of Poly-Si Film Grain Size by Excimer Laser Annealing and Its Application to High-Performance Poly-Si Thin Film Transistor

Abstract: By both numerical simulation and experimental investigation, we found it possible to enlarge the grain size (?3000 ?) of polycrystalline silicon (poly-Si) films by excimer laser annealing, using a new method to control the solidification process of molten Si - low-temperature (?400?C) substrate heating during laser annealing. Poly-Si thin-film transistors (TFTs) fabricated by this new excimer laser annealing method showed a high field-effect mobility of 230 cm2/V?s, and good uniformity of field-effect mobility (?10%) within the effective laser irradiation area.

Performance of thin hydrogenated amorphous silicon thin‐film transistors

Abstract: In this paper we have analyzed the influence of the mask channel length (LM) on the performance of the 55‐nm‐hydrogenated amorphous silicon (a‐Si:H) thin‐film transistors (TFTs), incorporating nitrogen‐rich hydrogenated amorphous silicon nitride gate dielectric and phosphorus‐doped microcrystalline silicon (n+μc‐Si:H) source/drain (S/D) contacts. In our TFTs the n+μc‐Si:H S/D contacts have a specific contact resistance around or below 0.5 Ω cm2. We have shown that in our TFTs a field‐effect mobility and threshold voltage are dependent on LM, and this dependence is most likely due to the influence of the S/D contact series resistance on TFTs characteristics. Finally, we have demonstrated that if the mask channel length is extended by a ΔL (which is a distance from the S/D via edge at which the electron injection/collection is taking place) the field‐effect mobility and threshold voltage are independent of the channel length. In such a case μFE, VT, and ON/OFF current ratio around 0.76 cm2/V s, 2.5 V, and 1...

Switched capacitor analog circuits using polysilicon thin film technology

Abstract: Switched capacitor analog circuits (such as integrators, amplifiers and digital-to-analog converters) constructed from polysilicon thin film transistors and capacitors are disclosed. The circuits are commonly implemented using conventional single crystal CMOS technologies, but this is the first time they have been realized using polysilicon TFT CMOS. The performance of the circuits is inevitably worse than that of conventional single crystal CMOS devices, but is nevertheless adequate for many large area applications. The circuits can be fabricated on large area substrates and integrated with, for example, flat panel displays, pagewidth optical scan arrays, or pagewidth printheads, offering improvements in the functionality and performance of those devices. Charge redistribution amplifiers and digital-to-analog converters are shown to operate with settling times ranging from a few microseconds to a few tens of microseconds, even with large capacitive loads, despite the relatively poor performance of polysilicon TFTs in comparison to conventional MOSFETS. Better than 8-bit accuracy is also demonstrated for the digital-to-analog converters.

Thin-film transistor

Abstract: PURPOSE:To reduce the dispersion of the breakdown strength of a gate insulating film and prevent deterioration thereof, and to obviate the disconnection of a source electrode and a drain electrode by burying the stepped section of a gate electrode with phosphosilicate glass and forming a tapered surface, in which stepped sections are decreased. CONSTITUTION:A phosphosilicate glass film 3 is formed onto a glass substrate 1, on which a gate electrode 2 is formed, through a spin-on method, a gate insulating film 4 and an amorphous intrinsic silicon film 5 are formed thereon and a source electrode 7 and a drain electrode 7 are formed on an amorphous n silicon 6 at both sides of a section located above the gate electrode 2. Accordingly, the stepped sections of the side faces of the gate electrode are filled by the phosphosilicate glass film formed through a spin-on method after the gate electrode is shaped, thus preventing the generation of a constriction and a flaw in the gate insulating film formed to the upper layers of the stepped sections of the gate electrode, the amorphous intrinsic silicon film, the amorphous n silicon film, the source electrode and the drain electrode, then acquiring uniform film quality.

Avalanche-induced effects in polysilicon thin-film transistors

Abstract: A comparison of experimental data and two-dimensional numerical simulations of polysilicon thin-film transistors (TFTs) is presented. It is shown that avalanche multiplication causes both the kink effect in the output characteristics and the reduction of threshold voltage in short-channel device. It is shown that exactly the same physical model for avalanche multiplication gives very good agreement between simulations and experimental data for both these effects. It is demonstrated that it is the presence of grain boundaries or traps in the polysilicon that causes avalanche effects to be much greater than in comparable single-crystal silicon devices. >

Active matrix substrate

Abstract: There is disclosed an active matrix substrate including on a given substrate a thin film transistor, a scanning line connected to the gate of the thin film transistor, a data bus connected to the source of the thin film transistor, and a picture element electrode connected to the data bus through the thin film transistor, the active matrix substrate comprising a structure of the scanning line having the surface covered with an insulating film. A semiconductor layer covered with a gate insulating film constituting the thin film transistor, and a gate electrode constituting the thin film transistor, which are laid on each other in the stated order.

High-temperature thin-film diamond field-effect transistor fabricated using a selective growth method

Abstract: Selective growth of boron-doped homoepitaxial diamond films was achieved using sputtered SiO/sub 2/ as a masking layer. The hole mobility of selectively grown films varied between 210 and 290 cm/sup 2//V-s for hole concentration between 1.0*10/sup 14/ and 6.9*10/sup 14/ cm/sup -3/. The technique was used to fabricate a thin-film diamond field-effect transistor operational at 300 degrees C. The channel resistance of the device is an exponential function of temperature. In combination with the selective growth method, this device can be used as a starting point for the development of high-temperature diamond-based integrated circuits. >

Silicon carbide field-effect transistor with improved breakdown voltage and low leakage current

Abstract: A silicon carbide field-effect transistor is provided which includes a semiconductor substrate, a channel formation layer of silicon carbide formed above the substrate, source and drain regions provided in contact with the channel formation layer, a gate insulator disposed between the source and drain regions, and a gate electrode formed on the gate insulator, wherein a first contact between the channel formation layer and the drain region exhibits different electric characteristics from those of a second contact between the channel formation layer and the source region. Also provided is a method for producing such a silicon carbide field-effect transistor.

Method for fabricating high mobility thin film transistors as integrated drivers for active matrix display

Abstract: High mobility thin film transistors for fabricating integrated drivers for active matrix displays and a special method of fabrication for obtaining the thin film transistors having mobility sufficiently high enough as drivers operable in the several megahertz frequency range needed for driving high resolution active matrix displays.

Measurement of threshold voltages of thin-film accumulation-mode PMOS/SOI transistors

Abstract: Accumulation-mode PMOS transistors on SOI (silicon on insulator) are characterized by several conduction mechanisms. Measurements of the threshold voltage corresponding to each of them are presented for the first time. An intuitive physical interpretation of their dependence on the front- and back-gate voltages is also given. >

Method for making an improved high voltage thin film transistor having a linear doping profile

Abstract: An improvement in a self-passivated high voltage semiconductor device is set forth with a thinned SOI layer having a linear lateral doping region coated with an oxide layer and a field plate being a part of the gate electrode layer. A high voltage SOI semiconductor device is formed having freedom from external electric fields.

Double DRAM cell

Abstract: A double dynamic random access memory (DRAM) cell comprising two vertically stacked access transistors and storage capacitors. A first access transistor is formed on a silicon substrate. A seed contact to the first access transistor is then utilized for growing an intermediate silicon substrate by Confined Lateral Selective Epitaxial Overgrowth (CLSEG). A second access transistor is formed upon the intermediate silicon substrate. A storage capacitor for the first access transistor may be formed as a trench capacitor in the silicon substrate. A storage capacitor for the second access transistor may be stacked on the second access transistor. A common buried bit line connects the two access transistors.

A method for the fabrication of low leakage polysilicon thin film transistors

Abstract: A method of manufacturing a thin film transistor having a low leakage current including depositing a layer of silicon oxide on a semiconductor substrate or on a layer of silicon nitrate deposited on a glass substrate, depositing a polysilicon layer, at a temperature of 520°-570° C., on the silicon oxide layer, annealing this polysilicon layer in a nitrogen atmosphere at a temperature of less than 650° C., forming islands in this polysilicon layer, forming a gate oxide layer on one of the islands by oxidizing the island under high pressure at a temperature below 650° C., forming a gate from a heavily doped polysilicon layer deposited on the gate oxide layer, forming lightly doped source and drain areas laterally adjacent to the gate, providing a thin layer of silicon oxide on the gate and the source and drain access, heavily doping areas of the first silicon layer adjacent to the source and drain areas, annealing the source and drain areas at a temperature below 650° C. and hydrogenating the resistive transistor with a hydrogen plasma.

Characterization of instability in amorphous silicon thin‐film transistors

Abstract: Instability mechanism of amorphous silicon‐silicon nitride thin‐film transistors (TFTs) is examined. By investigating double‐layer insulator TFTs, it is demonstrated that the instability is caused by an electrical charge stored at the interface between amorphous silicon and silicon nitride. The amount of stored charge at the interface (Q) does not depend on either drain voltage or drain current. Study on TFTs with several insulator thicknesses has shown that Q strongly depends on the band bending in the amorphous silicon that is related to the gate electric field (E) through the gate insulator. The Q‐E relationship is found to be a more general expression of the dependence of threshold voltage shift on gate voltage, and is incorporated into a formula suitable for examining the interface quality.

High performance thin film transistor (TFT) by solid phase epitaxial regrowth

Abstract: The present invention introduces a method to fabricate an active PMOS thin film transistor (or p-ch TFT) having an epitaxially grown channel region for high performance operation characteristics. Typically this p-ch TFT device would be fabricated overlying an NMOS active device, thereby becoming an active load (or pullup) to an NMOS device used is such applications as creating a memory cell in static random access memories (SRAMs). Conductivity types (p-type or n-type) may be interchanged to construct an n-ch TFT coupled with a PMOS active device if so desired. The fabrication of the TFT of the present invention may be used to form a CMOS inverter or simply an active pullup device when integrated into conventional CMOS fabrication processes.

High mobility poly-Si TFT by a new excimer laser annealing method for large area electronics

Abstract: A high-mobility (280 cm/sup 2//V-s), high-throughput poly-Si TFT (thin-film transistor) formed using a low-temperature process ( >

Low Temperature Poly-Si TFTs Using Solid Phase Crystallization of Very Thin Films and an Electron Cyclotron Resonance Chemical Vapor Deposition Gate Insulator

Abstract: Low temperature (T600°C) polycrystalline silicon thin film transistors (poly-Si TFTs) have been fabricated by solid phase crystallization (SPC) of amorphous silicon (a-Si) films deposited by low pressure chemical vapor deposition (LPCVD). These TFTs are distinguished by the very thin nature of the channel Si layer (25 nm) and the use of an SiO2 gate insulator deposited by electron cyclotron resonance chemical vapor deposition (ECR-CVD). The present process eliminates the need for hydrogenation and produces mobilities greater than 20 cm2/Vs and on/off current ratios greater than 107.

Method of testing active matrix liquid crystal display substrates

Abstract: A testing method for active matrix liquid crystal display substrates having thin film transistors provided with a plurality of pixel electrodes, a plurality of source lines, and a plurality of gate lines formed on a substrate. A high resolution electro-optical element whose optical properties change when an electrical field is impressed on it is disposed above the active matrix liquid crystal display substrate and separated therefrom by an extremely small gap. Electric current is caused to flow between the pixel electrodes on the active matrix liquid crystal display substrate and the transparent thin film electrodes on the surface of the electro-optical element, creating an electrical field in the electro-optical element. By detecting local changes in the optical properties of the electro-optical element, defects in the pixels of the active matrix liquid crystal display substrate can be detected.

Characterisation of low temperature poly-Si thin film transistors

Abstract: There is developing interest in using thin film transistors as active elements in a range of large area electronics applications The characteristics of poly-Si thin film transistors (TFTs), processed at glass compatible temperatures, have been investigated The particular features examined were the leakage current, hydrogenation mechanism and mobility The hydrogenation was found to proceed by a lateral penetration through the gate oxide around the edges of the poly-Si gate finger This led to a channel length dependence of sub-threshold slope in partially hydrogenated devices In contrast, the leakage current, which was shown to be a generation current at the drain junction, did not require hydrogen penetration into the centre of the channel and hence passivation of the generation centres was channel length independent The hydrogen diffusion coefficient in fine grain poly-Si was estimated at 350°C to be ∼1–10 × 10 −14 cm 2 / s depending upon the detailed material properties Thermal crystallisation of LPCVD and PECVD amorphous silicon was found to be comparable with both leading to large dendritic grains and enhanced carrier mobility

Liquid crystal display device with TFT's each including a Ta gate electrode and an anodized Al oxide film

Abstract: An active matrix liquid crystal display device with a plurality of thin-film transistors each including a gate electrode of an upper aluminum film and a lower tantalum film formed over a glass substrate and a gate insulator of an upper silicon nitride film and a lower anodized oxide film of the aluminum film.

PMOS transistors in LPCVD polycrystalline silicon-germanium films

Abstract: P-channel MOS thin-film transistors (TFTs) have been fabricated in low-pressure chemical vapor deposition (LPCVD) polycrystalline silicon-germanium (poly-SiGe) films using either a low-temperature ( >

Manufacturing method for SOI-type thin film transistor

Abstract: An SOI-type thin film transistor having a transparent insulating substrate a first gate electrode, a first gate insulating film, a semiconductor layer, a second gate electrode and a second gate insulating film which are respectively formed on the transparent insulating substrate, wherein the width of the first gate electrode and that of the second gate electrode are different from each other and as well as the thickness of the first gate insulating film and that of the second gate insulating film are different from each other

Low temperature germanium-silicon on insulator thin-film transistor

Abstract: MOS transistors are formed in thin films of Ge/Si alloys (Ge x Si 1-x ). According to the process of the present invention, polycrystalline films of Ge/Si are deposited using commercially-available LPCVD equipment, which in the preferred process uses silane and germane as the sources of Ge and Si. The deposited Ge x Si 1-x films are polycrystalline at temperatures for processing down to as below 400° C., and the films can be doped heavily by ion implantation and annealing at temperatures as low as 600° C. to give high mobility and dopant activation yielding very low resistivity. By carrying out the annealing step in the formation of the thin film transistors in the temperature range of 400° to 500° C., the films provide very large grain size, minimizing the impact of grain boundaries in the polycrystalline films where the thin film transistors are to be formed. As a result, thin film MOS transistors are fabricated at temperatures below 500° C., and as low as 400° C., by using Ge x Si 1-x deposition and doping technology. The resulting transistors have significantly improved electrical characteristics compared to thin film transistors fabricated in silicon films utilizing standard processing techniques.

Positive control of the source/drain-gate overlap in self-aligned tfts via a top hat gate electrode configuration

Abstract: Positive control over the length of the overlap between the gate electrode and the source and drain electrodes in a thin film transistor is provided by a gate conductor layer comprising two different conductors having differing etching characteristics. As part of the gate conductor pattern definition process, both gate conductors are etched to expose the underlying material and the upper gate conductor layer is etched back to expose the first gate conductor layer in accordance with the desired overlap between the gate electrode and the source and drain electrodes. Thereafter, the remainder of the device is fabricated with the source and drain electrodes self-aligned with respect to the second gate conductor layer using a planarization and non-selective etch method.

Low leakage current offset-gate thin film transistor structure

Abstract: A thin film transistor structure and methods of manufacture provide high ON/OFF current ratio and significantly reduce OFF state leakage currents. A doped thin film disposed on an insulating substrate is etched to form opposing source and drain regions. An undoped thin film is disposed between the opposing source and drain regions so that there is some overlap of the undoped thin film onto the top sides of the source and drain regions. Conventional photomasking, etching and ion implantation steps are then used to form a gate electrode offset from at least the drain region, and preferably offset from both source and drain regions, as well as conventional insulation and interconnect layers. The reduction in electric field intensity in the drain region, and the reduction in trap state density result from, performing heavy junction doping prior to deposition of the undoped thin film, and offsetting the gate electrode from the drain region. This structure provides very low OFF state leakage current while not seriously affecting the ON current. Several alternative fabrication processes are disclosed.