Journal ArticleDOI
PMOS transistors in LPCVD polycrystalline silicon-germanium films
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P-channel MOS thin-film transistors (TFTs) have been fabricated in low-pressure chemical vapor deposition (LPCVD) polycrystalline silicon-germanium (poly-SiGe) films using either a low-temperature ( >Abstract:
P-channel MOS thin-film transistors (TFTs) have been fabricated in low-pressure chemical vapor deposition (LPCVD) polycrystalline silicon-germanium (poly-SiGe) films using either a low-temperature ( >read more
Citations
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Journal ArticleDOI
Polycrystalline silicon thin films processed with silicon ion implantation and subsequent solid-phase crystallization: Theory, experiments, and thin-film transistor applications
Noriyoshi Yamauchi,Rafael Reif +1 more
TL;DR: In this article, a review of the self-implantation method for polycrystalline silicon thin transistors is presented, and the mechanism of selective amorphization by the silicon self implantation and the crystallization by thermal annealing is discussed.
Journal ArticleDOI
High-performance germanium-seeded laterally crystallized TFTs for vertical device integration
TL;DR: In this article, Germanium is used as a seeding agent at the source and/or drain of thin film transistors (TFTs) to laterally crystallize amorphous silicon films, resulting in high performance devices.
Journal ArticleDOI
Stability of C54 titanium germanosilicide on a silicon-germanium alloy substrate
D. B. Aldrich,Y. L. Chen,Dale E. Sayers,Robert J. Nemanich,Stanton P. Ashburn,Mehmet C. Öztürk +5 more
TL;DR: The stability of C54 Ti(Si1−yGey)2 films in contact with Si1−xGex substrates was investigated in this article, where it was determined that initially the Si diffuses to the C54 grain boundaries where it combines with Si from the substrate and precipitates as Si 1−zGez which is Ge•rich relative to the substrate.
Patent
Process for improving roughness of conductive layer
TL;DR: In this paper, a surface seeding method for fabricating hemispherical grained (HSG) silicon layers is described, where an amorphous silicon layer is doped with germanium.
Journal ArticleDOI
Solid phase crystallization of amorphous Si1−xGex films deposited on SiO2 by molecular beam epitaxy
TL;DR: In this article, solid phase crystallization behavior of the molecular beam epitaxy grown amorphous Si1−xGex (x=0 to 0.53) alloy layers using x-ray diffractometry and transmission electron microscopy (TEM) was investigated.
References
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Journal ArticleDOI
Anomalous leakage current in LPCVD PolySilicon MOSFET's
TL;DR: The anomalous leakage current I L in LPCVD polysilicon MOSFETs is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain, and an analytic model that describes the strong dependences of I L on the gate and drain voltages is developed.
Journal ArticleDOI
Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon
Satwinder Malhi,Hisashi Shichijo,Sanjay K. Banerjee,R. Sundaresan,M. Elahy,Gordon P. Pollack,William F. Richardson,Ashwin H. Shah,L.R. Hite,R.H. Womack,Pallab K. Chatterjee,H.W. Lam +11 more
TL;DR: In this paper, a design methodology was developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools.
Journal ArticleDOI
Polysilicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film
TL;DR: In this paper, a poly-Si thin-film transistors with channel dimensions comparable to or smaller than the grain size of the polySi film were fabricated and characterized, and a remarkable improvement was observed in the device characteristics as the channel dimensions decreased to W=L=2 mu m. The improvement was attributed to a reduction in the effect of the grain boundaries and to the effect on the device's floating body.
Journal ArticleDOI
Avalanche-induced effects in polysilicon thin-film transistors
M. Hack,A.G. Lewis +1 more
TL;DR: In this paper, a comparison of experimental data and two-dimensional numerical simulations of polysilicon thin-film transistors is presented, and it is shown that avalanche multiplication causes both the kink effect in the output characteristics and the reduction of threshold voltage in short-channel device.
Proceedings ArticleDOI
Future trends for TFT integrated circuits on glass substrates
H. Ohshima,S. Morozumi +1 more
TL;DR: The main objective is to realize sufficient electrical characteristics of TFT devices below 600 degrees C, using methods such as MOS interface control, crystalline grain growth, and trap passivation at grain boundaries, which will make it possible to apply TFT circuits not only to much larger substrates but also to concepts such as three-dimensional LSIs.