Showing papers on "VHDL published in 1999"

VHDL-AMS-a hardware description language for analog and mixed-signal applications

Abstract: This paper provides an overview of the VHDL-AMS hardware description language for analog and mixed-signal applications, by describing the major elements of the language and illustrating them by examples.

Multithreaded, mixed hardware description languages logic simulation on engineering workstations

Abstract: This invention describes a multithread HDL logic simulator that is unique from the prior arts. Specifically, it can process both VHDL and Verilog languages in a single program, and it uses special concurrent algorithms to accelerate the tool's performance on multiprocessor platforms to achieve linear to super-linear scalability on multiprocessor systems. Furthermore, the invention includes a unique remote logic simulation and job scheduling capabilities.

Macro-based hardware compilation of Java/sup TM/ bytecodes into a dynamic reconfigurable computing system

Abstract: This paper presents a new approach to synthesize to reconfigurable hardware (HW) user-specified regions of a program, under the assumption of "virtual HW" support. The automation of this approach is supported by a compiler front-end and by an HW compiler under development. The front-end starts from the Java bytecodes and, therefore, supports any language that can be compiled to the JVM (Java Virtual Machine) model. It extracts from the bytecodes all the dependencies inside and between basic blocks. This information is stored in representation graphs more suitable to efficiently exploit the existent parallelism in the program than those typically used in high-level synthesis. From the intermediate representations the HW compiler exploits the temporal partitions at the behavior level, resolves memory access conflicts, and generates the VHDL descriptions at register-transfer level that will be mapped into the reconfigurable HW devices.

Program Slicing of Hardware Description Languages

Abstract: Hardware description languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in formal verification, design, simulation, and testing. Program slicing is a static program analysis technique that allows an analyst to automatically extract portions of programs relevant to the aspects being analyzed. We extend program slicing to HDLs, thus allowing for automatic program reduction to allow the user to focus on relevant code portions. We have implemented a VHDL slicing tool composed of a general inter-procedural slicer and a front-end that captures VHDL execution semantics. This paper provides an overview of program slicing, a discussion of how to slice VHDL programs, a description of the resulting tool, and a brief overview of some applications and experimental results.

UML-based analysis of embedded systems using a mapping to VHDL

Abstract: Methods for developing and modeling embedded systems and rigorously verifying behavior before committing to code are increasingly important. A number of object-oriented techniques and notations have been introduced but recently, it appears that the Unified Modeling Language (UML) could be a notation broad enough in scope to represent a variety of domains and gain widespread use. Currently, however, UML is only a notation, with no formal semantics attached to the individual diagrams. In order to address this problem, we have developed a framework for deriving VHDL specifications from the class and state diagrams in order to capture the structure and the behavior of embedded systems. The derived VHDL specifications enable us to perform behavior simulation of the UML models.

Towards a visual modeling approach to designing microelectromechanical system transducers

Abstract: In this paper, we address initial design capture and system conceptualization of microelectromechanical system transducers based on visual modeling and design. Visual modeling frames the task of generating hardware description language (analog and digital) component models in a manner similar to the task of generating software programming language applications. A structured topological design strategy is employed, whereby microelectromechanical foundry cell libraries are utilized to facilitate the design process of exploring candidate cells (topologies), varying key aspects of the transduction for each topology, and determining which topology best satisfies design requirements. Coupled-energy microelectromechanical system characterizations at a circuit level of abstraction are presented that are based on branch constitutive relations and an overall system of simultaneous differential and algebraic equations. The resulting design methodology is called visual integrated-microelectromechanical VHDL-AMS interactive design (VHDL-AMS is visual hardware design language for analog and mixed signal).

Automatic architectural synthesis of VLIW and EPIC processors

Abstract: This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing (EPIC) processor architectures starting from an abstract specification of their desired functionality. The process of architecture design makes concrete decisions regarding the number and types of functional units, number of read/write ports on register files, the data-path interconnect, the instruction format, its decoding hardware, and the instruction unit data-path. The processor design is then automatically synthesized into a detailed RTL-level structural model in VHDL along with an estimate of its area. The system also generates the corresponding detailed machine description and instruction format description that can be used to retarget a compiler and an assembler respectively. All this is part of an overall design system, called Program-In-Chip-Out (PICO), which has the ability to perform automatic exploration of the architectural design space while customizing the architecture to a given application and making intelligent, quantitative, cost-performance tradeoffs.

Method for testability analysis and test point insertion at the rt-leve l of a hardware development language (hdl) specification

Abstract: A method of producing a synthesizable RT-Level VHDL specification for input to a synthesis tool to generate a gate-level circuit having testability enhancement, the method comprising the steps of developing a synthesizable RT-Level VHDL specification representative of said circuit, analyzing said VHDL specification to produce a VHDL Intermediate Format (VIF) representation; transforming said VIF representation into a Directed Acyclic Graph (DAG); performing testability analysis on said Directed Acyclic Graph by computing and propagating Testability Measures (TMs) forward and backward through VHDL statements of said Directed Acyclic Graph; identifying the bits of each signals/variables on which faults are hard to detect; and performing test point insertion in said specification at the RT-Level by adding new VHDL test statements to improve testability.

A low-power Viterbi decoder design for wireless communications applications

Abstract: Viterbi decoders employed in digital wireless communications are complex and dissipate large amount of power. In this paper, we investigate power dissipation for three different implementations of the Viterbi algorithm for wireless communications applications, including our proposed low-power Viterbi decoder. The schemes employed in our low-power design are clock-gating and toggle filtering. We described the behavior of three Viterbi decoders in VHDL and synthesized using a synthesis tool. The synthesized circuits were placed and routed in the standard cell design environment. Power estimation obtained through gate level simulations indicates that the proposed design reduces the power dissipation of an original Viterbi decoder design by 55%.

Digital Systems Design with VHDL and Synthesis: An Integrated Approach

Abstract: DESCRIPTION K.C. Chang presents an integrated approach to digital design principles, processes, and implementations to help the reader design increasingly complex systems within shorter design cycles. Chang introduces digital design concepts, VHDL coding, VHDL simulation, synthesis commands, and strategies together. Digital Systems Design with VHDL and Synthesis focuses on the ultimate product of the design cycle: the implementation of a digital design. Many of the design techniques and considerations illustrated in the text are examples of actual real-world designs.

Digital Systems Design with VHDL and Synthesis

Abstract: From the Publisher: K. C. Chang presents an integrated approach to digital design principles, processes, and implementations to help the reader design increasingly complex systems within shorter design cycles. Chang introduces digital design concepts, VHDL coding, VHDL simulation, synthesis commands, and strategies together. Digital Systems Design with VHDL and Synthesis focuses on the ultimate product of the design cycle: the implementation of a digital design. Many of the design techniques and considerations illustrated in the text are examples of actual real-world designs.

Cycle and phase accurate DSP modeling and integration for HW/SW co-verification

Abstract: We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with other hardware and software components. A common approach to the modeling of processors for HW/SW co-verification relies on instruction-accurate ISA models combined (i.e. wrapped) with the bus interface model (BIM) that generate the clock/phase-accurate timing at the component's interface pins. However, for DSPs and new microprocessors with complex architectural features this approach is from our perspective not acceptable. The additional extensive modeling of the pipeline and other architectural details in the BIM would force us to develop two detailed processor models with a complex BIM API between them. We therefore propose an alternative approach in which the processor ISAs themselves are modeled in a full cycle/phase-accurate fashion. The bus interface model is then reduced to just modeling the connection to the pins. Our models have been integrated into a number of cycle-based and event-driven system simulation environments. We present one such experience in incorporating these models into a VHDL environment. The accuracy has been verified cycle-by-cycle against the gate/RTL level models. Multiprocessor debugging and observability into the precise cycle-accurate processor state is provided. The use of co-verification models in place of the RTL resulted in system speedups up to 10 times, with the cycle-accurate ISA models themselves reaching performances of up to 123 K cycles/s.

Symbolic functional vector generation for VHDL specifications

Abstract: Verification of the functional correctness of VHDL specifications is one of the primary and most time consuming tasks of design. However, it must necessarily be an incomplete task since it is impossible to completely exercise the specification by exhaustively applying all input patterns. The paper aims at presenting a two-step strategy based on symbolic analysis of the VHDL specification, using a behavioral fault model. First, we generate a reduced number of functional test vectors for each process of the specification which allows complete code statement coverage and bit coverage, allowing the identification of possible redundancies in the VHDL process. Then, through the definition of a controllability measure, we verify if these functional test vectors can be applied to the process inputs when interconnected to other processes. If this is not the case, the analysis of the nonapplicable inputs provides identification of possible code redundancies and design errors. Experimental results show that bit coverage provides complete statement coverage and a more detailed identification of possible design errors.

A design framework for asynchronous/synchronous circuits based on CHP to HDL translation

Abstract: An open design framework, which allows mixing asynchronous and synchronous circuit styles, is presented. It is based on the development of a tool called "CHP/sub 2/VHDL" which automatically translates CSP-like specifications (Communicating Sequential Processes) into VHDL programs. This work follows two main motivations: (i) to provide the asynchronous circuit designers with a powerful execution/simulation framework mixing high-level CSP descriptions, HDL programs and gate level descriptions, (ii) to give to synchronous designers familiar with existing HDL-based top-down design flows, the opportunity to include clockless circuits in their designs. An extension of the CHP language proposed by A.J. Martin (1990) is presented and its simulation-oriented features are discussed. The "CHP/sub 2/VHDL" translator and its software environment are then described. Finally, a significant design experiment is considered to illustrate the efficiency of the design framework.

Formal verification of word-level specifications

Abstract: Formal verification has become one of the most important steps in circuit design. In this context the verification of high-level Hardware Description Languages (HDLs), like VHDL, becomes increasingly important. In this paper we present a complete set of datapath operations that can be formally verified based on Word-Level Decision Diagrams (WLDDs). Our techniques allow a direct translation of HDL constructs to WLDDs. We present new algorithms for WLDDs for modulo operation and division. These operations turn our to be the core of our efficient verification procedure. Furthermore, we prove upper bounds on the representation size of WLDDs guaranteeing effectiveness of the algorithms. Our verification tool is totally automatic and experimental results are given to demonstrate the efficiency of our approach.

Interval Temporal Logic

Abstract: The dynamic semantics of VHDL presented in this book is based on Allen’s Interval Temporal Logic [4]. This chapter presents some of the key concepts of this logic. Interval Logic is useful in capturing the timing information contained in a VHDL description. The logic organizes a universe by time intervals, relations between time intervals, and by binding actions (or assertions) to time intervals. VHDL behavior can be defined in terms of time intervals and a set of actions that are performed in these time intervals.

A compact fast variable key size elliptic curve cryptosystem coprocessor

Abstract: Elliptic curve (EC) cryptosystems have become more attractive due to their small key sizes and varieties of choices of the curves available. However, it is not efficient to implement them with a general-purpose microprocessor because of word size mismatch, less parallel computation, no hardware supported wire permutation and algorithm/architecture mismatch. The solution to this problem is to build a coprocessor. This coprocessor can be optimized for the algorithm of a particular application to enhance performance. Thus, the total hardware utilization can be kept at a very high rate and the computation is speeded up. A compact fast elliptic curve crypto coprocessor with variable key size is introduced, which utilizes the internal SRAM/registers in an FPGA. The generic hardware architecture for the coprocessor is implemented with a parameterized (in term of key size) VHDL description and is synthesized/mapped to a Xilinx FPGA. The algorithms adopted and the architecture developed are suitable for massively parallel computation. The experimental results show that the design can achieve a high utilization of CLBs for the Xilinx 4000 series.

Behavioral fault modeling in a VHDL synthesis environment

Abstract: This paper proposes new fault models for VHDL behavioral descriptions of combinational logic circuits. The models are developed via abstraction of industry standard single-stuck-line (SSL) faults into the behavioral domain. A functional analysis technique is used to evaluate the effects of SSL faults on gate level implementations. Generalized functional faults are then abstracted into the behavioral domain by examining their relationship with the higher level language construct. Test vectors derived from the new behavioral fault models are applied to synthesized gate level realizations of an example arithmetic logic unit. Resulting gate level fault coverage is determined and used as a measure of effectiveness for the new fault models. Because the behavioral faults are derived from a functional analysis of low level faults, they provide improved fault coverage over previous fault models.

Modelling and Synthesis of Configuration Controllers for Dynamically Reconfigurable Logic Systems Using the DCS CAD Framework

Abstract: The overheads contributed to a dynamically reconfigurable logic (DRL) design by its configuration controller can be prohibitive. Not only are the resource requirements and execution delays of the dynamic design adversely effected, but the time to redesign and test a configuration controller for every design iteration can be significant. We present a generic model of a configuration controller. The model is sufficiently complex to be useful in many design scenarios, and is customisable via parameterisation and user defined blocks. A new tool, DCSConfig, has been created within the DCS CAD framework to provide partial automation of configuration controller design. The new CAD tool provides initial estimates of latency and complexity overheads. VHDL models of the configuration controller for a particular dynamic design are produced for simulation and hardware synthesis.

Design and synthesis of an IEEE-754 exponential function

Abstract: We have designed a floating-point exponential function using the table-driven method. The algorithm was first implemented using sequential VHDL and later translated to Concurrent Verilog. The main part of the work consisted of creating modules that would handle basic IEEE-754 single-precision number manipulation routines, such as addition, multiplication and rounding to the nearest integer. Using these routines, a model was implemented based on the table-driven algorithm. The VHDL design as well as the Verilog design were estimated, and the results proved to be satisfactory. Synthesis was performed using CMOSIS5 technology on the VHDL code and yielded a fairly large result.

C for system level design

Abstract: Few people disagree with the fact that today about 80% of a system is software running on a "platform" of general purpose or custom processors (CPU and/or DSP) tightly coupled with unique dedicated hardware. This makes C (or C++) an obvious candidate for a system level design language. Without good hardware/software partitioning tools and support for C-based hardware design, the software content may have to increase by necessity. With the right hardware support a system team has the flexibility to make cost, performance, power trade-offs and decide later in the game how much of the system is software and how much is hardware. Another issue is legacy software and hardware. Legacy C software is well understood but legacy hardware is usually only available as RTL (Verilog or VHDL) at best. Therefore the ideal system level design language is C (or C++) based, accommodates hardware design but also co-exists with the vast legacy of Verilog and VHDL based re-usable hardware. CoWare N2C is practical solution, used in real life design around the world, that a) preserves the C software development paradigm for software people, b) adds the necessary clocking to C to enable hardware designers to move C functionality into a hardware architecture, and c) co-exists C for co-design and co-simulation) with existing hardware in Verilog or VHDL.

Challenges in processor modeling and validation [Guest Editors' introduction]

Abstract: The methodology for designing state-of-the-art microprocessors involves modeling at various levels of abstraction. In the pre-synthesis phase, this can range from early-stage (microarchitectural) performance-only models to final-stage, detailed register-transfer-level (RTL) models. Hierarchical modeling requires the use of an elaborate validation methodology to ensure inter- and intra-level model integrity. The RTL model, often coded in a hardware description language (e.g. Verilog or VHDL) captures the logical behavior of the entire chip: both in terms of function and cycle-by-cycle pipeline flow timing. It is this model that is subjected to simulation-based architectural validation prior to actual "tape-out" of the processor. The validated RTL specification is used as the source reference model for synthesizing the gate- and circuit-level descriptions of the processor.

Simulink/Matlab-to-VHDL Route for Full-Custom/FPGA Rapid Prototyping of DSP Algorithms

Abstract: This paper presents the way of speeding up the route from the theoretical design with Simulink/Matlab, via behavioral simulation in fixed-point arithmetic to the implementation on either FPGA or custom silicon. This has been achieved by porting the netlist of the Simulink system description into the VHDL. At the first instance, the Simulink-to-VHDL converter has been designed to use structural VHDL code to describe system interconnections, allowing simple behavioral descriptions for basic blocks. The resulting VHDL code delivers bit-true result when compared to the equivalent fixed-point Simulink model simulations.

Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST

Abstract: This paper proposes a new testability analysis and test-point insertion method at the register transfer level (RTL), assuming a full scan and a pseudorandom built-in self-test design environment. The method is based on analyzing the RTL synchronous specification in synthesizable very high speed integrated circuit hardware descriptive language (VHDL). A VHDL intermediate form representation is first obtained from the VHDL specification and then converted to a directed acyclic graph (DAG) that represents all data dependencies and flow of control in the VHDL specification. Testability measures (TMs) are computed on this graph. The considered TMs are controllability and observability for each bit of each signal/variable that is declared or may be implied in the VHDL specification. Internal signals of functional modules (FMs) such as adders and comparators are also analyzed to compute their controllability and observability values. The internal signals are obtained by decomposing at the RTL large FMs into smaller ones. The calculation of TMs is carried out at a functional level rather than the gate level, to reduce or eliminate errors introduced by ignoring reconvergent fanouts in the gate network, and to reduce the complexity of the DAG construction. Based on the controllability/observability values, test-point insertion is performed to improve the testability for each bit of each signal/variable. This insertion is carried out in the original VHDL specification and thus becomes a part of it unlike in other existing methods. This allows full application of RTL synthesis optimization on both the functional and the test logic concurrently within the designer constraints such as area and delay. A number of benchmark circuits were used to show the applicability and the effectiveness of our method in terms of the resulting testability, area, and delay.

An application of FPGA to high-speed programmable controller: development of the conversion program from SFC to Verilog

Abstract: The high-speed programmable controller (PC) is required in factory automation (FA). Recently, field programmable gate arrays (FPGA) are expected to be used for high-speed PC. Programming languages for a current PC are Ladder Diagram or Sequential Function Chart (SFC). On the other hand, programming languages for a FPGA are VHDL or Verilog-HDL. The authors have therefore developed a conversion program from SFC to Verilog-HDL. The paper reports on the conversion program.

A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine

Abstract: A formal semantic analysis for Verilog-HDL and VHDL is provided in order to give the simulation model especially focusing on signal scheduling and timing control mechanism. Our semantics is faithful to LRM and is expected to become a coherent first step for a future semantic interoperability analysis on multisemantic-domain such as Verilog-ARMS and VHDL-AMS. By ignoring the differences of the two simulation cycles, we can use the common semantic functions and the common simulation cycle.

Sassy: A Language and Optimizing Compiler for Image Processing on Reconfigurable Computing Systems

Abstract: This paper presents Sassy, a single-assignment variant of the C programming language developed in concert with Khoral Inc. and designed to exploit both coarse-grain and fine-grain parallelism in image processing applications. Sassy programs are written in the Khoros software development environment, and can be manipulated inside Cantata (the Khoros GUI). The Sassy language supports image processing with true multidimensional arrays, sophisticated array access and windowing mechanisms, and built-in reduction operators (e.g. histogram). At the same time, Sassy restricts C so as to enable compiler optimizations for parallel execution environments, with the goal of reducing data traffic, code size and execution time. In particular, the Sassy language and its optimizing compiler target re-configurable systems, which are fine-grain parallel processors. Reconfigurable systems consist of field-programmable gate arrays (FPGAs), memories and interconnection hardware, and can be used as inexpensive co-processors with conventional workstations or PCs. The compiler optimizations needed to generate highly optimal host, FPGA, and communication code, are discussed. The massive parallelism and high throughput of reconfigurable systems makes them well-suited to image processing tasks, but they have not previously been used in this context because they are typically programmed in hardware description languages such as VHDL. Sassy was developed as part of the Cameron project, with the goal of elevating the programming level for reconfigurable systems from hardware circuits to programming language.

Implementation of ladder diagram for programmable controller using FPGA

Abstract: Sequential control is an elementary technology for manufacturing systems. Manufacturing devices or systems are usually controlled by programmable controllers (PCs). In order to satisfy the requirements of downsizing and hidden information, we develop a novel type of controller which is implemented using the field programmable gate array (FPGA) as an application specific integrated circuit (ASIC). The widely used programming language in the area of sequential control, Ladder Diagram (LD), is also implemented on such a FPGA. The main bottleneck of the implementation is how to realize cyclic scan, which is the most significant characteristic of PCs. We describe two methods to implement the cyclic scan. One involves using the clock event of the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL), and the other is of translating a coil as a self-hold circuit of LD into an appropriate flip-flop element of VHDL. We also compare the two methods and show the benefits of the new controller implemented by FPGA.

Digital implementation of artificial neural networks: From VHDL description to FPGA implementation

Abstract: This paper deals with a top down design methodology of an artificial neural network (ANN) based upon parametric VHDL description of the network. To come off early in the design process a high regular architecture was achieved. Then, the VHDL parametric description of the network was realized. The description has the advantage of being generic, flexible and can be easily changed at the user demand. To validate our approach, an ANN for electrocardiogram (ECG) arrhythmia's classification is passed through a synthesis tool, GALILEO, for FPGA implementation.