J
Jack T. Kavalieros
Researcher at Intel
Publications - 353
Citations - 10336
Jack T. Kavalieros is an academic researcher from Intel. The author has contributed to research in topics: Transistor & Layer (electronics). The author has an hindex of 55, co-authored 351 publications receiving 10238 citations. Previous affiliations of Jack T. Kavalieros include Metz.
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Patent
Tri-gate devices and methods of fabrication
TL;DR: In this paper, a gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the SINR, which is a semiconductor device consisting of a top surface and laterally-opposite sidewalls formed on a substrate.
Journal ArticleDOI
Integrated nanoelectronics for the future
TL;DR: Given feature sizes as small as a few nanometres, what will the future hold for integrated electronics?
Patent
Non-planar gate all-around device and method of fabrication thereof
Rachmady Willy,Ravi Pillarisetty,Le Van H,Jack T. Kavalieros,Robert S. Chau,Jessica S. Kachian +5 more
TL;DR: In this paper, a non-planar gate all-around device and method of fabrication was described, which includes a substrate having a top surface with a first lattice constant and a bottom gate isolation is formed on the top surface of the substrate under the bottom most channel nanowire.
Patent
Method for making a semiconductor device having a high-k gate dielectric
Mark L. Doczy,Gilbert Dewey,Suman Datta,Sangwoo Pae,Justin K. Brask,Jack T. Kavalieros,Matthew V. Metz,Adrian B. Sherrill,Markus Kuhn,Robert S. Chau +9 more
TL;DR: In this paper, a method for making a semiconductor device is described, which comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer.
Patent
Block Contact Architectures for Nanoscale Channel Transistors
Marko Radosavljevic,Amlan Majumdar,Brian S. Doyle,Jack T. Kavalieros,Mark L. Doczy,Justin K. Brask,Uday Shah,Suman Datta,Robert S. Chau +8 more
TL;DR: In this article, a contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies is presented.