Journal ArticleDOI
Variation Caused by Spatial Distribution of Dielectric and Ferroelectric Grains in a Negative Capacitance Field-Effect Transistor
Ming-Yen Kao,Angada B. Sachid,Yen-Kai Lin,Yu-Hung Liao,Harshit Agarwal,Pragya Kushwaha,Juan Pablo Duarte,Huan-Lin Chang,Sayeef Salahuddin,Chenming Hu +9 more
TLDR
In this article, a new scheme was proposed to consider the dielectric (DE) phases inside polycrystalline ferroelectric (FE) materials, and a Sentaurus TCAD structure was constructed with the extracted parameters, and the simulated P-E curve was in a good agreement with the experimental data.Abstract:
We propose a new scheme to consider the dielectric (DE) phases inside polycrystalline ferroelectric (FE) materials. The scheme is used to extract material parameters from experimental polarization-electric field (P-E) measurements from the literature. A Sentaurus TCAD structure is constructed with the extracted parameters, and the simulated P-E curve is in a good agreement with the experimental data. Furthermore, variation of the device performance in a negative capacitance field-effect transistor (NCFET) due to the spatial distribution of DE and FE phases is studied using Sentaurus TCAD. It is found that the resultant variations of on and off currents can be up to 14.44% and 30.23%, respectively, thus showing the impact of inhomogeneous crystalline phases of the FE material on device performance.read more
Citations
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Journal ArticleDOI
Proposal for Capacitance Matching in Negative Capacitance Field-Effect Transistors
Harshit Agarwal,Pragya Kushwaha,Yen-Kai Lin,Ming-Yen Kao,Yu-Hung Liao,Avirup Dasgupta,Sayeef Salahuddin,Chenming Hu +7 more
TL;DR: A new approach using multi-layer FE to engineer the shape of negative-capacitance field-effect transistor is discussed, and the results show that it leads to better sub-threshold swing as well as lower power supply.
Journal ArticleDOI
Variability Analysis for Ferroelectric FET Nonvolatile Memories Considering Random Ferroelectric-Dielectric Phase Distribution
You-Sheng Liu,Pin Su +1 more
TL;DR: In this paper, the impact of the random ferroelectric-dielectric (FE-DE) phase distribution on the memory window (MW) of the Ferroelectric field effect transistor (FeFET) nonvolatile memory (NVM) with the aid of TCAD atomistic simulations was investigated.
Journal ArticleDOI
Grain Size Engineering of Ferroelectric Zr-doped HfO 2 for the Highly Scaled Devices Applications
TL;DR: In this article, the grain properties of 12-nm-thick HZO films are investigated and optimized by altering the atomic layer deposition (ALD) cycle ratio of HfO2 and ZrO2 at a constant Zr concentration.
Journal ArticleDOI
A memory window expression to evaluate the endurance of ferroelectric FETs
TL;DR: In this article, an analytical expression for the Memory Window (MW) is proposed to evaluate the endurance of nonvolatile memories based on ferroelectric transistors (FeFETs), which is defined as the difference between threshold voltages occurring due to polarization switching.
Journal ArticleDOI
Optimization of NCFET by Matching Dielectric and Ferroelectric Nonuniformly Along the Channel
Ming-Yen Kao,Yen-Kai Lin,Harshit Agarwal,Yu-Hung Liao,Pragya Kushwaha,Avirup Dasgupta,Sayeef Salahuddin,Chenming Hu +7 more
TL;DR: In this paper, a new design to overcome the nonuniformity of capacitance matching along the channel of a negative capacitance field effect transistor is presented, in which the thickness of SiO2 at the edge regions of the channel can be increased while maintaining the thickness at the center region.
References
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Journal ArticleDOI
Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices
Sayeef Salahuddin,Supriyo Datta +1 more
TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal Article
Negative Capacitance in a Ferroelectric Capacitor
Asif Islam Khan,Korok Chatterjee,Brian Wang,Steven Drapcho,Long You,Claudy Serrao,Saidur Rahman Bakaul,Ramamoorthy Ramesh,Sayeef Salahuddin +8 more
TL;DR: In this paper, negative capacitance in a thin epitaxial ferroelectric film was observed to decrease with time, in exactly the opposite direction to which voltage for a regular capacitor should change.
Journal ArticleDOI
The effects of crystallographic orientation and strain of thin Hf0.5Zr0.5O2 film on its ferroelectricity
TL;DR: In this paper, the effects of film strain and crystallographic orientation on the properties of Hf0.5Zr 0.5O2 films were examined using a (111)-textured Pt bottom electrode.
Proceedings ArticleDOI
Sub-60mV-swing negative-capacitance FinFET without hysteresis
Kai-Shin Li,Pin-Guang Chen,Tung-Yan Lai,Chang-Hsien Lin,Cheng-Chih Cheng,Chun-Chi Chen,Yun-Jie Wei,Yun-Fang Hou,Ming-Han Liao,Min-Hung Lee,Min-Cheng Chen,Jia-Min Sheih,Wen-Kuan Yeh,Fu-Liang Yang,Sayeef Salahuddin,Chenming Hu +15 more
TL;DR: In this article, negative-Capacitance FinFETs with a floating internal gate are reported, where ALD Hf042ZrO2 ferroelectricity is added on top of the gate stack.
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