C
C. Vizioz
Researcher at French Alternative Energies and Atomic Energy Commission
Publications - 32
Citations - 529
C. Vizioz is an academic researcher from French Alternative Energies and Atomic Energy Commission. The author has contributed to research in topics: CMOS & Nanowire. The author has an hindex of 13, co-authored 32 publications receiving 479 citations.
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Method of manufacturing a buried-gate semiconductor device and corresponding integrated circuit
TL;DR: In this article, a gate region is formed by forming a cavity under the channel region and an annealing step is performed so as to form a silicide of said metal in the cavity.
Proceedings ArticleDOI
First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers
Laurent Brunet,Perrine Batude,Claire Fenouillet-Beranger,P. Besombes,L. Hortemel,F. Ponthenier,Bernard Previtali,Claude Tabone,A. Royer,C. Agraffeil,C. Euvrard-Colnat,A. Seignard,Christophe Morales,F. Fournel,L. Benaissa,Thomas Signamarcheix,Pascal Besson,M. Jourdan,R. Kachtouli,V. Benevent,J.M. Hartmann,C. Comboroure,N. Allouti,Nicolas Posseme,C. Vizioz,Christian Arvet,Sébastien Barnola,Sebastien Kerdiles,L. Baud,L. Pasini,C.-M. V. Lu,F. Deprat,Alain Toffoli,G. Romano,C. Guedj,Vincent Delaye,Frederic Boeuf,O. Faynot,Maud Vinet +38 more
TL;DR: In this article, a full 3D CMOS over CMOS CoolCube integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain.
Proceedings ArticleDOI
First demonstration of strained SiGe nanowires TFETs with ION beyond 700µA/µm
A. Villalon,C. Le Royer,Pascal Nguyen,Sylvain Barraud,F. Glowacki,Alberto Revelant,Luca Selmi,Sorin Cristoloveanu,L. Tosti,C. Vizioz,J.M. Hartmann,Nicolas Bernier,Bernard Previtali,Claude Tabone,F. Allain,Sebastien Martinie,O. Rozeau,M. Vinet +17 more
TL;DR: In this article, the authors presented a high performance Nanowire (NW) Tunnel FET (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si 1-x¯¯Ge x (x=0, 0.2, 0., 0.25) nanowires, Si petertodd 0.7======Ge 0.3====== Source and Drain and High-K/Metal gate.
Proceedings ArticleDOI
3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics
Thomas Ernst,E. Bernard,Cecilia Dupre,Arnaud Hubert,S. Becu,Bernard Guillaumot,Olivier Rozeau,Olivier Thomas,Philippe Coronel,Jean-Michel Hartmann,C. Vizioz,Nathalie Vulliet,O. Faynot,Thomas Skotnicki,Simon Deleonibus +14 more
TL;DR: Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes and low IOFF and high ION transistors were demonstrated.
Proceedings ArticleDOI
Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors
K. Tachi,M. Casse,S. Barraud,Cecilia Dupre,Arnaud Hubert,Nathalie Vulliet,M.E. Faivre,C. Vizioz,C. Carabasse,Vincent Delaye,J.M. Hartmann,Hiroshi Iwai,Sorin Cristoloveanu,O. Faynot,Thomas Ernst +14 more
TL;DR: In this paper, the limiting scattering phenomena in gate-all-around nanowire CMOS transistors with aggressive dimensions (L eff of 32 nm for NMOS and 42 nm for PMOS) and with high-k/metal gate stacks were analyzed.