Showing papers by "Rao Tummala published in 2013"

Comparison of thermal performance between glass and silicon interposers

Abstract: This paper compares thermal performance of glass and silicon interposers for mobile applications, using computational modeling. It is well known that while silicon is a good thermal conductor, glass is a poor conductor, potentially making it unsuitable for packaging applications. This study proposes to address this short coming of glass by comparing and contrasting with silicon. In this study, for more accurate thermal analysis, effective thermal conductivity of glass interposer substrates is measured by infrared microscopy. Subsequently, equivalent thermal conductivity of TPV (Through Package Via) is calculated through numerical analyses. For comparison of thermal performance of glass and silicon interposers, 2.5D interposer structures with logic and memory chips are considered. The comparison shows that by incorporating thermal vias, junction temperature for the glass interposer decreases by about 60%, while junction temperature for silicon interposer decreases 45%, making both acceptable. However, the glass interposer provides significantly better thermal isolation between logic and memory chips. Glass and silicon interposer structures placed in enclosures, representative of mobile applications, provide comparable performance in the presence of thermal vias.

Ultra-miniaturized and surface-mountable glass-based 3D IPAC packages for RF modules

Abstract: This paper demonstrates ultra-miniaturized RF passive components integrated on thin glass substrate with small Through Package Vias (TPVs) to realize 3D Integrated Passive and Actives Component (IPAC) concept. Miniaturization is achieved through; a) ultra-thin glass, b) low-loss thin dielectrics and c) small TPVs. Inductors, capacitors and low pass filters functioning in the frequency range of 0.8 GHz to 5.4 GHz were modeled and fabricated between thin dielectric layers on 100 μm thin glass, and then assembled on PCB through BGA interconnections. The simulated results corroborated well with measured results, providing guidelines for RF module fabrication.

Thermomechanical and electrochemical reliability of fine-pitch through-package-copper vias (TPV) in thin glass interposers and packages

Abstract: This paper reports reliability of copper-plated through-package-vias (TPVs) in glass interposer by modeling and experimental validation using accelerated life tests. In this paper, both thermomechanical reliability and electrochemical reliability of fine-pitch TPVs in glass interposer were investigated. Thermomechanical reliability was investigated by developing finite element models to calculate the thermomechanical stresses and strains inside TPVs during thermal cycling tests with several glass and polymer liner combinations. Fatigue lifetime of TPVs in glass is predicted based on these simulation results and then validated using experiments. Test samples with daisy chains of TPVs are fabricated with different glass and polymer material combinations and subjected to accelerated temperature cycling tests to assess the thermomechanical reliability of TPVs in glass interposer. Resistance of each daisy chain is monitored using 4-point probe during cycling. It is observed that majority of test samples passed 1000 thermal cycles without any significant changes in electrical resistance. Cross-sectioning of TPV daisy chains that showed significant changes in resistance, revealed that failures were related to defects induced during copper plating in TPV side walls. Electrochemical migration reliability of TPVs in glass was investigated to study conductive anodic filament (CAF) resistance of glass at very small via spacing. Test samples with different material combinations were subjected to biased and highly accelerated stress temperature-humidity test (HAST) to assess electrochemical migration reliability of TPVs. After biased-HAST for 100 hours at 130°C, 85% relative humidity (RH) and 5 V DC, no CAF failures were detected in either of the two material combinations, indicating good insulation reliability under high temperature and humidity conditions.

Large silicon, glass and low CTE organic interposers to printed wiring board SMT interconnections using copper microwire arrays

Abstract: This paper reports SMT-compatible stress-relief microwire arrays in thin polymer carriers, as a unique, novel and low-cost solution for reliable board-level interconnections between large silicon, glass and low coefficient of thermal expansion (CTE) organic interposers and printed wiring boards. The microwire arrays are pre-fabricated in ultra-thin carriers using low-cost manufacturing processes such as laser vias and copper electroplating, which are then assembled onto the back of the interposer as a stress-relief interlayer. Such a structure is assembled onto the board using standard SMT processes. The microwire array results in dramatic reduction in solder stresses and strains, even with larger interposer sizes (20 mm × 20 mm), at finer pitch (300-400 microns), without the need for underfill. The parallel wire arrays result in low resistance and inductance, and therefore do not degrade the electrical performance. The scalability of the structures and the unique processes, from micro to nanowires, provides extendibility to finer pitch and larger package sizes. The first part of the paper describes the design of microwire array to meet the thermo-mechanical reliability requirements. Finite element method (FEM) was used to study the reliability of the interconnections to provide guidelines for the test vehicle design. Strip models were built to study the reliability of 400 μm-pitch interconnections with a 100 μm thick, 20 mm × 20 mm silicon interposer that was SMT-assembled onto an organic printed wiring board. The performance of the microwire array interconnection is compared with that of ball grid array (BGA) interconnection, in warpage, equivalent plastic strain and projected fatigue life. A unique set of materials and processes was used to demonstrate the low-cost fabrication of the microwire array. Flexible thermoplastic polyimide films were used as the polymer film carriers for the microwire interconnection structure. In the initial feasibility demonstration, 100 μm thick films with laminated copper foil on both sides of the dielectric were used. A 308 nm excimer laser source was used to ablate the via arrays in the polymer. The microwires were batch fabricated by bottom-up electrolytic plating through the polymer template. A low-cost approach to the microwire fabrication is thus demonstrated by partially releasing the wires with controlled etching of the polymer carrier.

Low cost, high performance, and high reliability 2.5D silicon interposer

Abstract: This paper presents the first demonstration of polycrystalline silicon interposers with fine pitch through package vias (TPV), with less than 5μm RDL lithography at 50μm pitch copper microbump assembly. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. The polycrystalline Si interposer with 100-200μm thick raw Si, obtained without any back-grind or polish, and double side processing, without the use of carriers, has the potential to reduce the cost of wafer-based Si interposers by 2× and up to 10× by scaling to large panels. Thick polymer liner reduces the electrical loss of TPVs dramatically, by an order of magnitude compared to TSVs with SiO2 liner. Initial reliability of TPVs at 150μm and 200μm pitch was demonstrated with daisy chains passing 1000 thermal cycles from -55°C to 125°C. The paper concludes with Cu-SnAg microbump assembly at 50μm pitch onto panel Si interposers with Cu-polymer RDL routing at 4-5μm line lithography.

A new approach to power integrity with thinfilm capacitors in 3D IPAC functional module

Abstract: This paper presents a new active and passive integration concept called 3D IPAC (Integrated Actives and Passives) to address the power integrity in high-performance and multifunctional systems. The 3D IPAC consists of an ultra-thin glass module with through-vias and double-side integration of ultra-thin active and passive components to form functional modules. By integrating power ICs, storage capacitors and inductors, and high-frequency decoupling capacitors in ultra-thin (30-100 μm) glass substrates, 3D IPAC Voltage Regulator Module (3D IPAC VRM) provides a complete and ultra-miniaturized solution to power integrity. The ultra-thin 3D IPAC allows both actives and passives very close to each other and to the other active dies, resulting in improved performance over conventional SMDs and state-of-art IPDs for decoupling functions. The first part of the paper presents modeling results to show the benefits of the 3D IPAC module as a power integrity solution. The second part of the paper presents the fabrication and characterization of high-k thinfilm capacitors and etched aluminum film capacitors integrated on either sides of a through-via 3D IPAC glass substrate. This paper, therefore, demonstrates the integration of heterogeneous capacitors on a single ultra-thin glass substrate for the first time, and presents its benefits as a complete solution for power integrity.

Multichip Embedding Technology Using Fine-Pitch Cu–Cu Interconnections

Abstract: Increasing performance and functional density while maintaining low cost is a catalyst for technological progress in the field of packaging. From flip-chip with solder to a hybrid approach of copper and solder, many methods have been created to reach this objective. The 3-D Packaging Research Center at Georgia Tech has been revolutionizing interconnection technology with the multichip embedding chip-last approach, which utilizes ultrathin adhesive-bonded copper bumps to enable ultrafine-pitch chip-to-package interconnections. This technology has been proven to be highly reliable using a low-cost low-temperature direct copper-to-copper bonding approach at 30-μm pitch and ~20-μm standoff height copper-to-copper interconnections. This interconnection method provides a platform for integration with flip-chip packages through its proven ability to work well with different die sizes and thicknesses bonded to the surface of ultrathin organic substrates. The next step in advancing the chip-last approach is to investigate chip embedding at the single-chip and multichip levels. Consequently, this paper focuses on: 1) the design and fabrication of the test vehicle to examine the reliability of the previously demonstrated copper-to-copper interconnections after embedding a thin die in an organic substrate, and 2) assembly process development and reliability data for the interconnections. Specifically, advances in the assembly process include: 1) a novel method to perform chip-last assembly at the panel level leading to a 10-15 times reduction in assembly time per die, and 2) an improved two-step assembly process to achieve simultaneous die embedding and cavity planarization. This embedding technology and its advancements not only allow actives to be embedded in organic substrates but also enables higher functional integration at high-throughput, making chip-last adhesive bonding with low-profile copper-to-copper interconnections a robust chip embedding solution for the next generation of highly integrated heterogeneous subsystems.

Modeling, design, and fabrication of ultra-high bandwidth 3D Glass Photonics (3DGP) in glass interposers

Abstract: This paper presents, for the first time, the 3D Glass Photonics (3DGP) technology being developed by Georgia Tech, based on ultra-thin 3D glass interposer [1]. The 3DGP system integrates both optical and electrical interconnects in the same glass substrate using photo-sensitive polymer core, and polymer cladding within an ultra-thin glass substrate. The 3DGP processes are demonstrated using 180 & 100 um thick glass substrates with 30 um diameter via and 8 um wide waveguide structures. The optical vias are used as mode transformer and high-tolerance coupler between fibers and chips. Finite-difference analysis is performed to determine the alignment tolerances of such vias.

Magnetic losses in metal nanoparticle-insulator nanocomposites

Abstract: Metal nanoparticle-insulator nanocomposites were synthesized and characterized for their magnetic loss and frequency-stability to understand the role of metal particle size and oxide passivation. Cobalt nanocomposites were synthesized with different matrices such as lead-borosilicate glass, silica and polymers, and fabricated into toroids for characterizing their microstructure and magnetic properties. X-ray Diffraction and Transmission Electron Miscroscopy were used to characterize the microstructure while Vibration Sample Magnetometry and impedance spectroscopy were used to obtain saturation magnetization, coercivity, permeability and magnetic loss. Nanocomposites with particles in the size range of 40–90 nm showed poor frequency stability and high loss beyond 200 MHz while finer particles (25–40 nm) resulted in stable properties beyond 500 MHz. The high coercivity and FMR broadening with oxide-passivated nanoparticle composites, however, degraded the magnetic losses at 500 MHz even with finer particles. The role of particle size and surface effects in suppressing the permeability and enhancing the frequency-stability is discussed.

Analysis of glass interposer PDN and proposal of PDN resonance suppression methods

Abstract: Electrical characteristics of glass interposer PDN is analyzed and compared with silicon interposer. Because of the low loss of glass substrate compared to silicon substrate, glass interposer has much smaller loss than silicon interposer. It helps low-loss signaling, but it generates sharp PDN resonance unlike silicon interposer. If glass interposer signal line has through-glass via (TGV), it experiences high loss at the resonance frequency. Also P/G noise is easily coupled to signal line and vice versa at that frequency. It would be problems for the glass interposer PDN design. To overcome these problems of glass interposer, several resonance suppression methods are proposed such as decoupling capacitor scheme, ground via.

Coelectrodeposited Solder Composite Films for Advanced Thermal Interface Materials

Abstract: A novel coelectrodeposition process was explored to form composite solder thin films as advanced bonding layers with potentially superior thermal and mechanical properties. The solder electrolyte was modified with SiC and graphite particles to electroplate the solder composite films. The stability of the particles was enhanced with cetyltrimethylammonium bromide (CTAB) as the surfactant. CTAB also enhanced the positive charge of the surface, measured as zeta potential, to further improve the electrophoretic deposition of the particles. Dynamic light scattering was used, for the first time, to characterize the particle size distribution and zeta potential for the graphite-tin electrolyte suspensions. Incorporation of CTAB enhanced the zeta potential from 17 to 33 mV and improved the particle dispersion resulting in much homogeneous plating with higher particle content in the films. X-ray diffraction, energy dispersive spectroscopy, and scanning electron microscopy were utilized to characterize the plated composites. Bonding was demonstrated with solder composites having high particle loading. Pressure-assisted bonding enhanced solder wetting on particles and improved the bonding characteristics.

Conductive Anodic Filament Failures in Fine-Pitch Through-Via Interconnections in Organic Package Substrates

Abstract: Failures due to conductive anodic filament (CAF) formation in copper-plated through-vias have been a concern in printed wiring boards since the 1970s. With the continuous reduction in through-via pitch to meet high circuit density demands in organic packages, the magnitude of CAF failures is expected to be significantly higher. In this study, an accelerated test condition [130°C, 85% relative humidity (RH), and 100 V direct current (DC)] was used to investigate CAF in two organic package substrates: (1) cyclo-olefin polymer–glass fiber composite (XR3) and (2) epoxy–glass fiber composite (FR4). Test coupons with through-via spacing of 100 μm and 200 μm were investigated in this study. CAF failures were not observed in either substrate type with spacing of 200 μm. With spacing of 100 μm, insulation failures were observed in FR4, while XR3 exhibited stable insulation resistance during the test. The substrates were characterized using gravimetric measurement, and XR3 was found to exhibit significantly lower moisture absorption compared with FR4. The CAF failures in FR4 were characterized using scanning electron microscopy and energy-dispersive x-ray spectroscopy. The results suggest a strong effect of moisture sorption of organic resins on CAF failure at smaller through-via spacing in package substrates.

Power delivery network analysis of 3D double-side glass interposers for high bandwidth applications

Abstract: Logic-to-memory interconnections by double-side mounting on ultra-thin 3D glass interposers with Through-Package-Vias (TPVs) achieves high bandwidth (BW) (>25.6GB per second), without the complex TSV processes in logic ICs, required for wide I/O 3D-IC stack. While this interposer/packaging technology offers several advantages including power delivery by enabling thick power-ground (P/G) planes, the power distribution network (PDN) challenges such as resonances must be addressed. This paper investigates the impedance characteristics of PDN in 3D glass interposers at chip, interposer, package, and board-levels. The resonance characteristics of power and ground planes in ultra-thin glass packages are compared with other interposer technologies through 3D EM simulations with variations in core thickness. Test vehicles fabricated with 10×10mm power-ground plane pairs on ultra-thin 30μm glass samples were characterized for primary resonance modes, with good model-to-hardware correlation. Self-impedance (Z11) was studied with variations in (a) number of power and ground BGA interconnections, (b) power and ground path distance, and (c) placement of decoupling capacitors. In all these three cases, the contribution of increased package-level loop inductance to total system level impedance (on-chip + interposer/package + PWB PDN) was shown to be minimal. Thus, through a combination of integrated power and ground planes, decoupling capacitors, and optimal power-ground BGA interconnection placements, ultra-thin 3D glass interposers can achieve the target impedance guidelines for high BW systems.

Conductive Anodic Filament Reliability of Small and Fine-Pitch Through Vias in Halogen-Free Organic Packaging Substrate

Abstract: The trend toward miniaturization of electronic systems demands reliable small fine-pitch through vias in organic packages and high-density interconnect system boards. Fine-pitch through vias in glass fiber-reinforced organic packages suffer from electrical insulation failures due to the formation of conductive anodic filaments (CAFs) in the presence of temperature, humidity, and voltage. In addition to the requirement for fine-pitch through vias, restriction in use of halogens as well as the move toward green electronic systems has driven the development of halogen-free thermally stable novel resin formulations for next-generation glass fiber-reinforced substrates. The introduction of new resin chemistries can also affect the reliability, as CAF failures are known to depend on the substrate material properties. In this paper, CAF reliability of small and fine-pitch through vias in a halogen-free glass fiber-reinforced organic substrate is investigated. Test structures with through via diameter of 100 μm with two different pitches, i.e., 250 and 500 μm , were fabricated and tested using 100 V direct current (dc) bias at 85 °C and 85% relative humidity for 1000 h. Insulation failures were observed in test structures with a pitch of 250 μm, while the test structures with a pitch of 500 μm exhibited stable insulation resistance during the test. Failures were identified using optical microscopy and characterized using scanning electron microscopy. The results indicate that CAF failures are a concern with fine-pitch through vias in packages, and, therefore, careful selection of materials and processes is required for achieving reliable fine-pitch through vias in high-density packages.

3D IPAC — A new passives and actives concept for ultra-miniaturized electronic and bioelectronic functional modules

Abstract: This paper describes an innovative 3D IPAC (Integrated Passive and Active Components) concept for ultra-miniaturized and highly-functional sub-systems, going beyond discrete passives and Integrated Passive Devices (IPDs). The 3D IPAC concept consists of an ultra-thin 3D structure made of low loss and ultra-thin glass substrates with small-diameter through-vias, and ultra-thin active devices and thin or thick passive films or thin discrete passives on both sides. The first part of the paper describes the benefits of the 3D IPAC concept. The second part of the paper describes a wireless power telemetry module for a bioelectronic system application, and provides proof-of-concept demonstrations for the thinfilm passive components as a building block in the 3D IPAC telemetry module.

All-Solution Thin-film Capacitors and Their Deposition in Trench and Through-Via Structures

Abstract: Thin integrated passive devices (IPDs) will play a critical role in the miniaturization of future high-performance electronic and bioelectronic systems. Silicon-based capacitors are currently manufactured with expensive processes such as sputtering and atomic layer deposition. Solution-deposited electrodes and dielectrics in trench and through-via structures provide alternative low-cost routes. Two solution-deposition techniques, spin-coating and vacuum infiltration, are investigated in this paper. A representative all-solution-derived thin-film capacitor consisting of sol-gel lanthanum nickel oxide (LNO) as the electrode, and sol-gel lead zirconate titanate as the dielectric thin-film is demonstrated in the first part of this paper. The role of barriers in reducing leakage currents is studied using three electrode systems: LNO/Si, LNO/ZrO2/Si, and LNO/Pt/Ta/Si. Capacitors with LNO electrodes directly deposited on naturally oxidized silicon resulted in higher leakages, more defects and a lower yield. The results show that the zirconia barrier suppresses the leakage current in the dielectric. The second part of this paper describes sol-gel films deposited in the through-via and trench surfaces to demonstrate the sol-gel conformal coating technique. Scanning electron microscopy cross-section analysis shows that the vacuum infiltration conformally coated through-vias. These solution deposition techniques may have the potential to fabricate IPD capacitors at low cost.

Printed circuit board (PCB) miniaturization by embedded passives and sequential build-up (SBU)process methodology

Abstract: One of the foremost design considerations in microelectronics miniaturization is the use of embedded passives which provide practical solution. In a typical circuit, over 80% of the electronic components are passives such as resistors, inductors, and capacitors that could take up to almost 50% of the entire printed circuit board area. By integrating passive components within the substrate instead of being on the surface, embedded passives reduce the system real estate, eliminate the need for discrete and assembly, enhance electrical performance and reliability. This paper presents an entire process from design and fabrication to electrical characterization and reliability test of embedded passives on multilayered microvia organic substrate. Numerical models of embedded capacitors have been developed to qualitatively examine the effects of process conditions and electrical performance due to thermo-mechanical deformations. Also, a prototype working product with the board-level design including features of embedded resistors and capacitors is presented.

Ultra-thin, self-healing decoupling capacitors on thin glass interposers using high surface area electrodes

Abstract: This paper presents a novel set of low-cost materials and processes to fabricate thinfilm decoupling capacitors on silicon and glass substrates, using printed valve-metal electrodes. The valve-metals such as Al and Ta allow for easy formation of conformal, robust and high insulation-strength dielectrics. By utilizing self-healing counter electrodes, high yield with low leakage currents were demonstrated. Such a thinfilm capacitor processing is compatible with large-area, high through-put glass substrates with through-vias. The process, therefore, allows double-side passive or active component integration in ultrathin substrates, leading to a unique and novel passive and active component integration technology referred to as 3D IPAC (3-Dimensional Integrated Actives and Passive components) for miniaturized and complete power or RF modules.

Ultra-thin and ultra-high I/O density package-on-package (3D Thin PoP) for high bandwidth of smart systems

Abstract: Package-on-package (PoP) technologies used in smart phones and tablets are reaching limits in logic-to-memory bandwidth and in thickness reduction. Advances in PoP including through-mold vias (TMVs) and low-CTE, high-modulus laminate substrates have not been able to overcome the I/O density and thickness limitations to date. To overcome these barriers, two major technologies have been pursued. The first approach is chip-first embedding in organic dielectrics and in fan-out wafer level packages. While this can achieve higher I/O's, they face many challenges that include large-die reliability, intermediate testability for higher yield, thermal dissipation, and new supply-chain model. The second approach to address the need is the so-called wide-I/O logic and memory stacking with through silicon vias (TSVs), which promises highest bandwidth in lowest profile, but is viewed as too complex and costly due to TSV integration in logic IC. Georgia Tech PRC proposes and demonstrates, for the first time, a third approach that is more manufacturable and cost-effective. This is referred to as 3D Thin PoP - a more advanced 3-dimensional POP, - designed to achieve ultra-thin stacked packages in 3D with higher chip-to package and package-to-package I/Os to achieve higher bandwidth. This paper reports a number of breakthrough advances in 3D Thin PoP, thus providing a path to extend PoP. These innovations fall into three areas that include: (a) Ultra-thin, 150μm thick organic substrate with multiple layers of build-up wiring with precision cavities ready for chip assembly, (b) die-to-package Cu-Cu interconnections at 30μm pitch bonded at 160°C, and (c) package-on-package stacking with 50μm interconnect pitch. Low signal losses are achieved by having shorter chip-to-chip I/O's and lower stand-off interconnections. These innovations enable higher bandwidth in 3D Thin PoP by virtue of 8× improvement in I/Os combined with 2-3× reduction in total thickness over current PoP.

RF Device Integration on Glass Interposer toward 3D-IPAC Packages

Abstract: 3D Integrated Passive and Actives Component (IPAC) is a new concept of ultra-miniaturized and highly functional sub-systems, which enables one to achieve higher RF functionality in a single module. As the first step, this paper demonstrates the concept of integrating passive components using 100μm ultra-thin glass and small Through Package Vias (TPVs) by ArF excimer laser. Passive low pass filters (LPF) for WLAN in thin dielectrics on glass were designed using circuit simulator and EM solver. The LPFs were fabricated using low-cost panel based processes, and then assembled onto the Printed Wiring Board (PWB). The filters on either side of the glass interposer were measured at the board level, and the results corroborated well with EM simulations. The measurement results showed low insertion loss (about −1dB) and high rejection (<−20dB). The integration of passive components using double-side and ultra-thin glass interposers with small TPVs, enables one to shrink RF module size.