The engineering of a compact qubit unit cell that embeds all quantum functionalities is mandatory for large-scale integration In addition, these functionalities should present the lowest error rate possible to successfully implement quantum error correction protocols1 Electron spins in silicon quantum dots are particularly promising because of their high control fidelity2–5 and their potential compatibility with complementary metal-oxide-semiconductor industrial platforms6,7 However, an efficient and scalable spin readout scheme is still missing Here we demonstrate a high fidelity and robust spin readout based on gate reflectometry in a complementary metal-oxide-semiconductor device that consists of a qubit dot and an ancillary dot coupled to an electron reservoir This scalable method allows us to read out a spin in a single-shot manner with an average fidelity above 98% for a 05 ms integration time To achieve such a fidelity, we combine radio-frequency gate reflectometry with a latched spin blockade mechanism that requires electron exchange between the ancillary dot and the reservoir We show that the demonstrated high readout fidelity is fully preserved up to 05 K This result holds particular relevance for the future cointegration of spin qubits and classical control electronics Gate reflectometry on an ancillary dot coupled to an electron reservoir is used to read the spin of a qubit in a CMOS device in a single shot with an average fidelity above 98% within 05 ms

Gate-based high fidelity spin readout in a CMOS device

Compute-in-memory (CIM) is a new computing paradigm that addresses the memory-wall problem in hardware accelerator design for deep learning. The input vector and weight matrix multiplication, i.e., the multiply-and-accumulate (MAC) operation, could be performed in the analog domain within memory sub-array, leading to significant improvements in throughput and energy efficiency. Static random access memory (SRAM) and emerging non-volatile memories such as resistive random access memory (RRAM) are promising candidates to store the weights of deep neural network (DNN) models. In this review, firstly we survey the recent progresses in SRAM and RRAM based CIM macros that have been demonstrated in silicon. Then we discuss general design challenges of the CIM chips including analog-to-digital conversion (ADC) bottleneck, variations in analog compute, and device non-idealities. Next we introduce the DNN+NeuroSim benchmark framework that is capable of evaluating versatile device technologies for CIM inference and training performance from software/hardware co-design's perspective.

Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects

3D monolithic integration of logic and memory has been the most sought after solution to surpass the Von Neumann bottleneck, for which a low-temperature processed material system becomes inevitable. Two-dimensional materials, with their excellent electrical properties and low thermal budget are potential candidates. Here, we demonstrate a low-temperature hybrid co-integration of one-transistor-one-resistor memory cell, comprising a surface functionalized 2D WSe2 p-FET, with a solution-processed WSe2 Resistive Random Access Memory. The employed plasma oxidation technique results in a low Schottky barrier height of 25 meV with a mobility of 230 cm2 V−1 s−1, leading to a 100x performance enhanced WSe2 p-FET, while the defective WSe2 Resistive Random Access Memory exhibits a switching energy of 2.6 pJ per bit. Furthermore, guided by our device-circuit modelling, we propose vertically stacked channel FETs for high-density sub-0.01 μm2 memory cells, offering a new beyond-Si solution to enable 3-D embedded memories for future computing systems. Designing efficient, scalable and low-thermal-budget 2D Materials for 3D integration remains a challenge. Here, the authors report the development of a hybrid-(solution-processed-exfoliated) integration of 2D Material based 1T1R which uses a multilayer WSe2 p-FET and a multilayer printed WSe2 RRAM.

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All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration.

In this work, we present a comprehensive theoretical and experimental study of quantum confinement in layered platinum diselenide (PtSe2) films as a function of film thickness. Our electrical measurements, in combination with density functional theory calculations, show distinct layer-dependent semimetal-to-semiconductor evolution in PtSe2 films, and highlight the importance of including van der Waals interactions, Green’s function calibration, and screened Coulomb interactions in the determination of the thickness-dependent PtSe2 energy gap. Large-area PtSe2 films of varying thickness (2.5–6.5 nm) were formed at 400 °C by thermally assisted conversion of ultra-thin platinum films on Si/SiO2 substrates. The PtSe2 films exhibit p-type semiconducting behavior with hole mobility values up to 13 cm2/V·s. Metal-oxide-semiconductor field-effect transistors have been fabricated using the grown PtSe2 films and a gate field-controlled switching performance with an ION/IOFF ratio of >230 has been measured at room temperature for a 2.5–3 nm PtSe2 film, while the ratio drops to <2 for 5–6.5 nm-thick PtSe2 films, consistent with a semiconducting-to-semimetallic transition with increasing PtSe2 film thickness. These experimental observations indicate that the low-temperature growth of semimetallic or semiconducting PtSe2 could be integrated into the back-end-of-line of a silicon complementary metal-oxide-semiconductor process.

/pdf/quantum-confinement-induced-semimetal-to-semiconductor-577nsb0fjd.pdf

Quantum confinement-induced semimetal-to-semiconductor evolution in large-area ultra-thin PtSe2 films grown at 400 °C

When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

Miniaturization of CMOS.

3D Sequential Integration (3DSI) with ultra-small 3D contact pitch (<100nm) offers new 3D partitioning options at fine granularities. This paper reviews potential applications ranging from computing to sensor interface and gives an update on 3DSI device development. Low-temperature processing techniques have made great progress and High Performance (HP) digital stacked FETs for computing application can be achieved with a 500°C Thermal Budget (TB). In addition, ULK/metal lines capable of withstanding this TB can be used between stacked tiers. Ultra-Low TB FETs (<400°C) have potential for low-power applications and allow for the stacking of multiple layers.

3D Sequential Integration: Application-driven technological achievements and guidelines

The 3D sequential integration, of active devices requires to limit the thermal budget of top tier processing to low temperature (LT) (i.e. $\mathrm{T}_{\text{TOP}}=500^{\circ}\mathrm{C})$ in order to ensure the stability of the bottom devices. Here we present breakthrough in six areas that were previously considered as potential showstoppers for 3D sequential integration from either a manufacturability, reliability, performance or cost point of view. Our experimental data demonstrate the ability to obtain 1) low-resistance poly-Si gate for the top FETs, 2) Full LT RSD epitaxy including surface preparation, 3) Stability of intermediate BEOL between tiers (iBEOL) with standard ULK/Cu technology, 4) Stable bonding above ULK, 5) Efficient contamination containment for wafers with Cu/ULK iBEOL enabling their re-introduction in FEOL for top FET processing 6) Smart Cut™ process above a CMOS wafer.

Breakthroughs in 3D Sequential technology

For the first time the thermal stability of a new fluorine-free (F-free) W barrier coupled with W interconnections enabling 22% line 1 resistance improvement is evaluated in view of 3D VLSI integration. Integrated with ULK, no resistance nor lateral capacitance degradation is observed up to 550°C 5h while preserving good reliability. For additional thermal stability a TEOS/W stability is demonstrated up to 600°C 2h. Both types of interconnection stacks have been successfully integrated on devices with 28nm design rules and show similar performance for MOSFETs and Ring Oscillators (RO) as compared to the ULK/Cu stack. Finally, iBEOL guidelines are given at the end in view of 3D sequential integration.

S. Beaurepaire

Papers

3D Sequential Integration: Application-driven technological achievements and guidelines

Breakthroughs in 3D Sequential technology

Guidelines for intermediate back end of line (BEOL) for 3D sequential integration