F
F. Aussenac
Researcher at Council for the Curriculum, Examinations & Assessment
Publications - 8
Citations - 150
F. Aussenac is an academic researcher from Council for the Curriculum, Examinations & Assessment. The author has contributed to research in topics: Laser & Nanowire. The author has an hindex of 7, co-authored 8 publications receiving 125 citations.
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Proceedings ArticleDOI
Breakthroughs in 3D Sequential technology
Laurent Brunet,C. Fenouillet-Beranger,Perrine Batude,S. Beaurepaire,F. Ponthenier,N. Rambal,V. Mazzocchi,J-B. Pin,P. Acosta-Alba,Sebastien Kerdiles,Pascal Besson,H. Fontaine,T. Lardin,F. Fournel,V. Larrey,F. Mazen,V. Balan,Christophe Morales,C. Guerin,Vincent Jousseaume,Xavier Federspiel,D. Ney,X. Garros,A. Roman,Daniel Scevola,P. Perreau,F. Kouemeni-Tchouake,Lucile Arnaud,C. Scibetta,S. Chevalliez,F. Aussenac,J. Aubin,Shay Reboh,Francois Andrieu,Sylvain Maitrejean,M. Vinet +35 more
TL;DR: In this article, the authors present breakthrough in six areas that were previously considered as potential showstoppers for 3D sequential integration from either a manufacturability, reliability, performance or cost point of view.
Journal ArticleDOI
Schottky Barrier Height Extraction in Ohmic Regime: Contacts on Fully Processed GeOI Substrates
Louis Hutin,C. Le Royer,Claude Tabone,Vincent Delaye,Fabrice Nemouchi,F. Aussenac,Laurent Clavelier,Maud Vinet +7 more
TL;DR: In this article, the Schottky barrier height (SBH) was measured on germanium metal-oxide-semiconductor field effect transistors with Ti-based contacts, yielding effective barriers of 0.32 eV and 0.15 eV for holes.
Proceedings ArticleDOI
Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width
R. Coquand,M. Casse,S. Barraud,P. Leroux,David K. C. Cooper,C. Vizioz,C. Comboroure,P. Perreau,V. Maffini-Alvaro,Claude Tabone,L. Tosti,F. Allain,Sébastien Barnola,Vincent Delaye,F. Aussenac,Gilles Reimbold,Gerard Ghibaudo,Daniela Munteanu,Stephane Monfray,Frederic Boeuf,O. Faynot,Thierry Poiroux +21 more
TL;DR: A detailed study of performance in uniaxially-strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial SSOI substrate is presented in this paper.
Proceedings ArticleDOI
High performance low temperature activated devices and optimization guidelines for 3D VLSI integration of FD, TriGate, FinFET on insulator
L. Pasini,Perrine Batude,M. Casse,B. Mathieu,Benoit Sklenard,F. Piegas Luce,Shay Reboh,Nicolas Bernier,Claude Tabone,O. Rozeau,S. Martini,Claire Fenouillet-Beranger,Laurent Brunet,G. Audoit,D. Lafond,F. Aussenac,F. Allain,G. Romano,S. Barraud,N. Rambal,V. Barral,Louis Hutin,J.M. Hartmann,Pascal Besson,Sebastien Kerdiles,Michel Haond,Gerard Ghibaudo,M. Vinet +27 more
TL;DR: In this article, the authors show that an extension first process scheme (implantation before the raised source and drain epitaxy) is required for FDSOI and TriGate architectures.
Proceedings ArticleDOI
Nanosecond Laser Annealing for Phosphorous Activation in Ultra-Thin Implanted Silicon-On-Insulator Substrates
P. Acosta Alba,Sebastien Kerdiles,B. Mathieu,R. Kachtouli,Fulvio Mazzamuto,I. Toque-Tresonne,Karim Huet,Pascal Besson,Marc Veillerot,F. Aussenac,C. Fenouillet-Beranger +10 more
TL;DR: In this article, it was shown that pulsed laser annealing (wavelength: 308 nm and pulse duration: 160 ns) allows the perfect crystal recovery of the implanted silicon layers.