Journal ArticleDOI
2.6 kV 4H-SiC lateral DMOSFETs
TLDR
In this paper, a 4H-SiC lateral double-implanted metal-oxide-semiconductor (LDMOS) field effect transistor is fabricated in a lightly doped n-epilayer on an insulating 4HSiC substrate.Abstract:
A 4H-SiC lateral double-implanted metal-oxide-semiconductor (LDMOS) field effect transistor is fabricated in a lightly doped n-epilayer on an insulating 4H-SiC substrate. After depleting through the epilayer, the depletion region continues to move laterally toward the drain. The result is an increase in blocking voltage compared to a vertical DMOSFET fabricated in the same epilayer on a conducting substrate. A blocking voltage of 2.6 kV is obtained, nearly double the highest previously demonstrated blocking voltage for a SiC MOSFET.read more
Citations
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Journal ArticleDOI
Status and prospects for SiC power MOSFETs
TL;DR: In this article, the authors review the evolution of SiC power MOSFETs between 1992 and the present, discuss the current status of device development, identify the critical fabrication issues, and assess the prospects for continued progress and eventual commercialization.
Journal ArticleDOI
Silicon carbide and diamond for high temperature device applications
TL;DR: The physical and chemical properties of wide bandgap semiconductors silicon carbide and diamond make these materials an ideal choice for device fabrication for applications in many different areas, e.g. light emitters, high temperature and high power electronics, high power microwave devices, micro-electromechanical system (MEMS) technology, and substrates as mentioned in this paper.
Journal ArticleDOI
High channel mobility in inversion layers of 4H-SiC MOSFETs by utilizing (112~0) face
TL;DR: In this article, an improvement of channel mobility in 4H-SiC MOSFETs was achieved by utilizing the (112~0) face: 17 times higher channel mobility than that on the conventional (0001) Si-face (5.59 cm/sup 2//Vs).
Journal ArticleDOI
Influence of epitaxial growth and substrate-induced defects on the breakdown of 4H–SiC Schottky diodes
Qamar Ul Wahab,Alexsandre Ellison,Anne Henry,Erik Janzén,Christer Hallin,J. Di Persio,R. Martinez +6 more
TL;DR: In this paper, the performance of 4H-SiC power devices with high voltage Ni Schottky diodes was investigated and morphological defects and elementary screw dislocations were found to severely limit the performance.
Journal ArticleDOI
Effects of wet oxidation/anneal on interface properties of thermally oxidized SiO/sub 2//SiC MOS system and MOSFET's
TL;DR: In this paper, the effects of wet atmosphere during oxidation and anneal on thermally oxidized p-type and n-type MOS interface properties were systematically investigated for both 4H- and 6H-SiC.
References
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Proceedings ArticleDOI
High voltage thin layer devices (RESURF devices)
J.A. Appels,H.M.J. Vaes +1 more
TL;DR: The RESURF (Reduced SURface Field) as discussed by the authors is a diode-based diode structure for high voltage devices with very thin epitaxial or implanted layers, where crucial changes in the electric field distribution occur at or at least near the surface.
Journal ArticleDOI
High-voltage double-implanted power MOSFET's in 6H-SiC
TL;DR: In this article, the first planar high-voltage MOSFET's in 6H-SiC were reported, with a block mode operation of up to 760 V, which is nearly three times higher than previously reported operating voltages for SiC MOS FET's.
Journal ArticleDOI
Progress in silicon carbide semiconductor electronics technology
TL;DR: In this article, the authors present the present status of SiC-based semiconductor electronics and identify areas where technological maturation is needed and the prospects for resolving these obstacles are discussed.
Journal ArticleDOI
Characterization and optimization of the SiO 2 /SiC metal-oxide semiconductor interface
Jayarama Shenoy,G. L. Chindalore,Michael R. Melloch,J.A. Cooper,John W. Palmour,K. G. Irvine +5 more
TL;DR: In this paper, the authors used the hilo capacitance-voltage technique and the ac conductance technique at elevated temperatures to characterize the MOS interface of p-type 6H-SiC.
Proceedings ArticleDOI
Dependence of breakdown voltage on drift length and buried oxide thickness in SOI RESURF LDMOS transistors
S. Merchant,Emil Arnold,Helmut Baumgart,R. Egloff,Theodore Letavic,Satyendranath Mukherjee,H. Pein +6 more
TL;DR: In this paper, the authors derived an ideal relationship between breakdown voltage and drift length, and showed that thin buried oxides are a major cause of deviation from this ideal, and an 860-V LDMOS transistor made in a 0.2 mu m-thick SOI layer is reported.