A 0.013mm 2 5μW DC-coupled neural signal acquisition IC with 0.5V supply

TLDR: This work presents a neural interface in 65nm CMOS and operating at a 0.5V supply that obtains performance comparable or superior to state-of-the-art systems in a silicon area over 3× smaller by using a scalable architecture that avoids on-chip passives and takes advantage of high-density logic.

Abstract: Recent success in brain-machine interfaces has provided hope for patients with spinal-cord injuries, Parkinson's disease, and other debilitating neurological conditions [1], and has boosted interest in electronic recording of cortical signals State-of-the-art recording solutions [2–5] rely heavily on analog techniques at relatively high supply voltages to perform signal conditioning and filtering, leading to large silicon area and limited programmability We present a neural interface in 65nm CMOS and operating at a 05V supply that obtains performance comparable or superior to state-of-the-art systems in a silicon area over 3× smaller These results are achieved by using a scalable architecture that avoids on-chip passives and takes advantage of high-density logic The use of 65nm CMOS eases integration with low-power digital systems, while the low supply voltage makes the design more compatible with wireless powering schemes [6]