Proceedings ArticleDOI
A 0.013mm 2 5μW DC-coupled neural signal acquisition IC with 0.5V supply
Rikky Muller,Simone Gambini,Jan M. Rabaey +2 more
- Vol. 47, Iss: 1, pp 302-304
TLDR
This work presents a neural interface in 65nm CMOS and operating at a 0.5V supply that obtains performance comparable or superior to state-of-the-art systems in a silicon area over 3× smaller by using a scalable architecture that avoids on-chip passives and takes advantage of high-density logic.Abstract:
Recent success in brain-machine interfaces has provided hope for patients with spinal-cord injuries, Parkinson's disease, and other debilitating neurological conditions [1], and has boosted interest in electronic recording of cortical signals State-of-the-art recording solutions [2–5] rely heavily on analog techniques at relatively high supply voltages to perform signal conditioning and filtering, leading to large silicon area and limited programmability We present a neural interface in 65nm CMOS and operating at a 05V supply that obtains performance comparable or superior to state-of-the-art systems in a silicon area over 3× smaller These results are achieved by using a scalable architecture that avoids on-chip passives and takes advantage of high-density logic The use of 65nm CMOS eases integration with low-power digital systems, while the low supply voltage makes the design more compatible with wireless powering schemes [6]read more
Citations
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Proceedings ArticleDOI
Compact chopper-stabilized neural amplifier with low-distortion high-pass filter in 0.13µm CMOS
Karim Abdelhalim,Roman Genov +1 more
TL;DR: A compact and low-distortion neural recording amplifier is presented that consists of two stages of amplification using capacitive feedback to set a gain of 54dB and is less sensitive to the output swing than the conventional sub-threshold MOS circuit.
Proceedings ArticleDOI
Microwire-CMOS integration of mm-scale neural probes for chronic local field potential recording
Katarzyna M. Szostak,Federico Mazza,Michal Maslik,Lieuwe B. Leene,Peilong Feng,Timothy G. Constandinou +5 more
TL;DR: A novel method for integrating CMOS microelectronics with microwire-based electrodes for next generation implantable brain machine interfaces is proposed using a new process flow utilising a recessed glass substrate for mechanical support, silicon interposer for interconnection, and electroplating for contact adhesion.
Journal ArticleDOI
Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product
TL;DR: A new index, the figure-of-merit (FoM)-delay (FD) product, is introduced to provide a balance between the energy efficiency and conversion speed to overcome the challenges associated with a reduced supply voltage.
Proceedings ArticleDOI
A 50 μW/Ch artifacts-insensitive neural recorder using frequency-shaping technique
TL;DR: A frequency-shaping neural recording interface that can inherently reject electrode offset, 5-10 times increase input impedance, 4.5-bit extend system dynamic range (DR), and provide much more tolerance to motion artifacts and 50/60 Hz power noise interferences is presented.
Journal ArticleDOI
A double-sided, single-chip integration scheme using through-silicon-via for neural sensing applications
Chih-Wei Chang,Lei Chun Chou,Po-Tsang Huang,Shang-Lin Wu,Shih Wei Lee,Ching-Te Chuang,Kuan-Neng Chen,Wei Hwang,Kuo Hua Chen,Chi Tsung Chiu,Ho Ming Tong,Jin-Chern Chiou,Jin-Chern Chiou +12 more
TL;DR: In-vivo long term implantation demonstrated the feasibility of presented integration scheme after 7 and 58 days of implantation, and it is expected the conceptual realization can be extended for higher density recording array by using the proposed method.
References
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Journal ArticleDOI
Brain–machine interfaces: past, present and future
TL;DR: This paper discusses designing a fully implantable biocompatible recording device, further developing real-time computational algorithms, introducing a method for providing the brain with sensory feedback from the actuators, and designing and building artificial prostheses that can be controlled directly by brain-derived signals.
Journal ArticleDOI
A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System
Reid R. Harrison,P.T. Watkins,R.J. Kier,R.O. Lovejoy,D. Black,Richard A. Normann,Florian Solzbacher +6 more
TL;DR: A prototype integrated circuit for wireless neural recording from a 100-channel microelectrode array was developed and a two-chip system was used to record neural signals from a Utah Electrode Array in cat cortex and transmit the digitized signals wirelessly to a receiver.
Journal ArticleDOI
A micropower low-noise monolithic instrumentation amplifier for medical purposes
Michiel Steyaert,Willy Sansen +1 more
TL;DR: A CMOS low-power low-noise monolithic instrumentation amplifier is described and it can produce variable gains of 14/20/26/40 dB, which are set by control software.
Journal ArticleDOI
An Energy-Efficient Micropower Neural Recording Amplifier
TL;DR: The amplifier appears to be the lowest power and most energy-efficient neural recording amplifier reported to date and the low-noise design techniques that help the neural amplifier achieve input-referred noise that is near the theoretical limit of any amplifier using a differential pair as an input stage.
Journal ArticleDOI
256-Channel Neural Recording and Delta Compression Microsystem With 3D Electrodes
J.N.Y. Aziz,Karim Abdelhalim,R. Shulyzki,Roman Genov,Berj L. Bardakjian,M. Derchansky,Demitre Serletis,Peter L. Carlen +7 more
TL;DR: Results of in vitro experimental recordings from intact mouse hippocampus validate the circuit design and the on-chip electrode bonding technology.
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