Journal ArticleDOI
A true single-phase-clock dynamic CMOS circuit technique
TLDR
The authors describe two dynamic circuit techniques, using only a single-phase clock which is never inverted, which has the advantages of simple clock distribution, small area for clock lines reduced clock skew problems, and high speed.Abstract:
The authors describe two dynamic circuit techniques, using only a single-phase clock which is never inverted. This class of circuits has the advantages of simple clock distribution, small area for clock lines reduced clock skew problems, and high speed. Several examples are demonstrated.read more
Citations
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Journal ArticleDOI
High-speed CMOS circuit technique
Jiren Yuan,Christer Svensson +1 more
TL;DR: It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process, and a precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used.
Journal ArticleDOI
Clock distribution networks in synchronous digital integrated circuits
TL;DR: A theoretical background of clock skew is provided and minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths.
Journal ArticleDOI
New single-clock CMOS latches and flipflops with improved speed and power savings
Jiren Yuan,Christer Svensson +1 more
TL;DR: In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.
Proceedings ArticleDOI
Single-rail handshake circuits
Anna Peeters,K. van Berkel +1 more
TL;DR: Single-rail handshake circuits are introduced as a cost effective implementation of asynchronous circuits that can be implemented in any (generic) standard-cell library and makes asynchronous circuits a potential technology of choice for low-power applications.
Journal ArticleDOI
A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors
F. Klass,Chaim Amir,A. Das,Kathirgamar Aingaran,C. Truong,R. Wang,A. Mehta,Raymond A. Heald,G. Yee +8 more
TL;DR: A new family of edge-triggered flip-flops has been developed that has the capability of easily incorporating logic functions with a small delay penalty, and greatly reduces the pipeline overhead.
References
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Journal ArticleDOI
NORA: a racefree dynamic CMOS technique for pipelined logic structures
N.F. Goncalves,H. De Man +1 more
TL;DR: A new dynamic CMOS technique which is fully racefree, yet has high logic flexibility, and logic inversion is provided, which means higher logic flexibility and less transistors for the same function.
Journal ArticleDOI
Fully Dynamic Switch-Level Simulation of CMOS Circuits
R. Sundblad,C. Svensson +1 more
TL;DR: A new algorithm for switch-level simulation is suggested which allows the simulator to be fully dynamic, i.e., several signals may propagate in the network simultaneously.
Journal ArticleDOI
A CMOS Design Strategy for Bit-Serial Signal Processing
A.F. Murray,P.B. Denyer +1 more
TL;DR: The design philosophy and style behind the CMOS cells are described, detailing the dynamic logic style used, its layout and testability, and a full-precision complex multiplier.
Journal ArticleDOI
A Design Style for VLSI CMOS
D.J. Myers,P.A. Ivey +1 more
TL;DR: A novel method for designing clocked dynamic CMOS that uses a four-phsse clocking scheme that is free from race and charge-sharing problems and results in faster, more compact layouts.
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New single-clock CMOS latches and flipflops with improved speed and power savings
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