Accelerated Publication: Electrical characteristics of a vertically integrated field-effect transistor using non-intentionally doped Si nanowires
Reads0
Chats0
TLDR
In this paper, the authors report the fabrication and electrical characterization of Vertical Gate All Around Field Effect Transistors (GAA-FET) using nonintentionally doped Silicon NanoWires (SiNWs) grown by Chemical Vapour Deposition (CVD) using the VLS mechanism as conduction channel.About:
This article is published in Microelectronic Engineering.The article was published on 2011-11-01 and is currently open access. It has received 19 citations till now. The article focuses on the topics: Field-effect transistor & Nanowire.read more
Citations
More filters
Journal ArticleDOI
Emerging Applications for High K Materials in VLSI Technology
TL;DR: The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed.
Journal ArticleDOI
Effect of HCl on the doping and shape control of silicon nanowires
Pascal Gentile,Amit Solanki,Nicolas Pauc,Fabrice Oehler,Bassem Salem,G. Rosaz,Thierry Baron,M. den Hertog,V. Calvo +8 more
TL;DR: A detailed study of the apparent resistivity of the NWs reveals that the dopant incorporation is effective for both types of doping, and a graph linking the apparentresistivity to the dopants to silane dilution ratio is built.
Journal ArticleDOI
pH driven addressing of silicon nanowires onto Si3N4/SiO2 micro-patterned surfaces.
Jean-Pierre Cloarec,Céline Chevalier,Céline Chevalier,Céline Chevalier,Jonathan Genest,Jacques Beauvais,Hassan Chamas,Yann Chevolot,Thierry Baron,Abdelkader Souifi,Abdelkader Souifi +10 more
TL;DR: A theoretical model based on DLVO theory and surface protonation/deprotonation equilibria was used to study how, in adequate pH conditions, Si nanowires could be anchored onto specific regions of a patterned Si3N4/SiO2 surface.
Journal ArticleDOI
Controlling the diameter of silicon nanowires grown using a tin catalyst
TL;DR: In this paper, the effect of the thickness of the thin film catalyst on the morphology of the silicon nanowires was investigated, and it was shown that the wire diameter increased as the thickness increased.
Journal ArticleDOI
Vertically integrated silicon-germanium nanowire field-effect transistor
TL;DR: In this article, the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field effect transistors (FETs) was demonstrated and a threshold voltage close to 3.9 V was reported.
References
More filters
Journal ArticleDOI
Ge/Si nanowire heterostructures as high-performance field-effect transistors
TL;DR: Comparison of the intrinsic switching delay, τ = CV/I, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFets.
Journal ArticleDOI
Silicon Vertically Integrated Nanowire Field Effect Transistors
TL;DR: In this paper, the authors demonstrate the direct vertical integration of Si nanowire arrays into surrounding gate field effect transistors without the need for postgrowth nanowires assembly processes.
Journal ArticleDOI
Single Crystal Nanowire Vertical Surround-Gate Field-Effect Transistor
TL;DR: In this paper, the authors demonstrate a bottom-up integration of a semiconductor 1D nanowire, using zinc oxide (ZnO) as an example, to obtain a vertical surround-gate field effect transistor (VSG-FET).