Area and power efficient high speed voltage comparator

TLDR: It is shown that the proposed dynamic comparator has good tradeoff between power consumption and delay with same sampling frequency and is proposed by removing few transistors to the conventional double-tail dynamic comparators to maximize speed and reduce power consumption.

Abstract: The need for high speed and low power analog-to-digital converters is pushing towards the use of power efficient dynamic regenerative comparator. A complete delay analysis on the double-tail dynamic comparators will be presented. Based on the calculated analysis a new dynamic comparator has proposed by removing few transistors to the conventional double-tail dynamic comparator to maximize speed and reduce power consumption. It is shown that the proposed comparator has good tradeoff between power consumption and delay with same sampling frequency. The comparator fabricated in 180nm CMOS process with clock frequency of 450 MHz at supply voltage 1.2 V consumes power of 37 pW.