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COSI: A Public-Domain Design Framework for the Design of Interconnection Networks

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TLDR
The COmmunication Synthesis Infrastructure (COSI), a public-domain design framework for the design exploration and synthesis of interconnection networks, is presented and a design for on-chip interconnect design is focused on.
Abstract
Alessandro Pinto, Luca P. Carloni and Alberto L. Sangiovanni-VincentelliThe COmmunication Synthesis Infrastructure (COSI), a public-domain designframework for the design exploration and synthesis of interconnection networks,is presented. The framework embodies a methodology based on the platform-based design principles and is used to de ne speci c design ows for a variety ofapplications. In this paper, we focus on a design ow for on-chip interconnectdesign.

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Proceedings ArticleDOI

Communication modeling for system-level design

TL;DR: In this article, the authors present accurate delay, power, and area models for bus-based and packet-switched communication architectures and integrate their models into the COSI-OCC system-level communication synthesis tool and show that the more accurate modeling significantly affects optimal/achievable architectures that are synthesized by the system level tool.
References
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The future of wires

TL;DR: Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays, which is good news since these "local" wires dominate chip wiring.
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Orion: a power-performance simulator for interconnection networks

TL;DR: Orion is presented, a power-performance interconnection network simulator that is capable of providing detailed power characteristics, in addition to performance characteristics, to enable rapid power- performance trade-offs at the architectural-level.
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Networks synthesis and optimum network design problems: Models, solution methods and applications

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Fixed-outline floorplanning: enabling hierarchical design

TL;DR: This paper studies the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs and proposes new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context.
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