Proceedings ArticleDOI
Decoupling capacitor calculations for CMOS circuits
L.D. Smith
- pp 101-105
Reads0
Chats0
TLDR
Capacitor values and quantities are calculated using time and frequency domain techniques in this article, where the authors propose a method for decoupling capacitors to reduce EMC/EMI radiated noise.Abstract:
CMOS circuits on printed circuit boards with continuous power planes require decoupling capacitors to keep power supply within specification, provide signal integrity and reduce EMC/EMI radiated noise. Capacitor values and quantities are calculated using time and frequency domain techniques.read more
Citations
More filters
Journal ArticleDOI
Power distribution system design methodology and capacitor selection for modern CMOS technology
TL;DR: In this paper, the impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models.
Journal ArticleDOI
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
TL;DR: Compared to postfloorplan approach, the peak power-supply noise can be reduced by as much as 40% and the decap budget can be reduction by asMuch as 21% by using noise-aware floorplanning methodology.
Journal ArticleDOI
High-capacity, self-assembled metal-oxide-semiconductor decoupling capacitors
Charles T. Black,Kathryn W. Guarini,Ying Zhang,H. Kim,J. Benedict,E. Sikorski,Inna V. Babich,Keith Raymond Milkove +7 more
TL;DR: In this paper, the authors combine nanometer-scale polymer self assembly with advanced semiconductor microfabrication to produce metaloxide-semiconductor (MOS) capacitors with accumulation capacitance more than 400% higher than planar devices of the same lateral area.
Journal ArticleDOI
Modeling, measurement, and simulation of simultaneous switching noise
Bradley McCredie,Wiren D. Becker +1 more
TL;DR: In this article, the authors present a high-frequency power distribution model for the simulation of simultaneous switching noise of a complementary metaloxide-semiconductor (CMOS) chip on a multilayered ceramic substrate.
Proceedings ArticleDOI
A novel integrated decoupling capacitor for MCM-L technology
TL;DR: In this paper, the design, materials, fabrication and measurements of a novel integrated decoupling capacitor for MCM-L-based substrates are discussed, with diameters of 100 um and below, through photodefinable processes.
References
More filters
Journal ArticleDOI
Decoupling capacitor effects on switching noise
TL;DR: In this paper, the decoupling capacitor efficiency in reducing the power supply differential switching noise of the multichip-module (MCM) package structure employed in the IBM ES/9000 system is described.
Journal ArticleDOI
Effectiveness of multiple decoupling capacitors
TL;DR: In this paper, the performance of parallel combination of large-value and small-value capacitors to increase the frequency coverage of either one and overcome the effect of lead inductance is examined.
Proceedings ArticleDOI
On the effectiveness of decoupling capacitors in reducing EM radiation from PCBs
S. Daijavad,H. Heeb +1 more
TL;DR: In this article, the effectiveness of using decoupling capacitors between power and ground planes in a typical PC or workstation printed circuit board (PCB) is studied from an electromagnetic compatibility (EMC) point of view.
Proceedings ArticleDOI
Advanced decoupling using ceramic MLC capacitors
TL;DR: In this article, the authors present a broad awareness that might reduce repetition and introduce a possible solution to the decoupling problem, noting that recent developments in high-speed decouplings have been in multiple simultaneous directions.
Proceedings ArticleDOI
CBGA vs. CQFP: electrical performance comparison and tradeoff study
Madhavan Swaminathan,L. Smith +1 more
TL;DR: This paper discusses the performance comparison between two types of packages namely the ceramic quad flat pack (CQFP) and ceramic ball grid array (CBGA) by including the details of the onchip metallization and second level (PCB) package parasitics.
Related Papers (5)
Power supply noise analysis methodology for deep-submicron VLSI chip design
Howard H. Chen,David D. Ling +1 more