Proceedings ArticleDOI
Design of high performance 64 bit MAC unit
P. Jagadeesh,S. Ravi,Kittur Harish Mallikarjun +2 more
- pp 782-786
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A design of high performance 64 bit Multiplier-and-Accumulator (MAC) is implemented in this paper and performs important operation in many of the digital signal processing (DSP) applications.Abstract:
A design of high performance 64 bit Multiplier-and-Accumulator (MAC) is implemented in this paper. MAC unit performs important operation in many of the digital signal processing (DSP) applications. The multiplier is designed using modified Wallace multiplier and the adder is done with carry save adder. The total design is coded with verilog-HDL and the synthesis is done using Cadence RTL complier using typical libraries of TSMC 0.18um technology. The total MAC unit operates at 217 MHz. The total power dissipation is 177.732 mW.read more
Citations
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Journal ArticleDOI
Low-Area wallace multiplier
Shahzad Asif,Yinan Kong +1 more
TL;DR: Synthesis results show that the proposed multiplier has the lowest area as compared to other tree-based multipliers, without compromising on the speed of the original Wallace multiplier.
Proceedings ArticleDOI
Design and performance analysis of Multiply-Accumulate (MAC) unit
TL;DR: MAC unit model is designed by incorporating the various multipliers such as Array Multiplier, Ripple Carry Array Multipler with Row Bypassing Technique, Wallace Tree Multipliers and DADDA MultiplIER in the multiplier module and the performance of MAC unit models is analyzed in terms of area, delay and power.
Proceedings ArticleDOI
High speed vedic multiplier used vedic mathematics
TL;DR: A Vedic multiplication algorithm is designed by using Vedic mathematics formula Urdhava Tiryakbhyam method means vertically and cross wise, which gets less time delay compared to other algorithms.
Journal ArticleDOI
Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis
TL;DR: The proposed circuit has 90% improvement in terms of power over complementary metal–oxide–semiconductor (CMOS) circuits and will give rise to a new thread of research in the field of real-time signal and image treatment.
References
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Journal Article
New VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm
Young-Ho Seo,Dong-Wook Kim +1 more
TL;DR: In this article, the authors proposed a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic, by combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved.
Journal ArticleDOI
A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
Young-Ho Seo,Dong-Wook Kim +1 more
TL;DR: The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency.
Journal ArticleDOI
Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers
TL;DR: This paper presents a technique to reduce by one row the maximum height of the partial product array generated by a radix-4 Modified Booth Encoded multiplier, without any increase in the delay of thepartial product generation stage, to allow for a faster compression of the Partial product array and regular layouts.