Journal ArticleDOI
Digital-domain calibration of multistep analog-to-digital converters
S.-H. Lee,B.-S. Song +1 more
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TLDR
A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs).Abstract:
A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs). While conventional self-calibration techniques require separate digital-to-analog converters (DACs) for calibration purpose to subtract nonlinearity errors in the analog domain, the proposed digital calibration technique uses add-on digital logic to subtract nonlinearity errors digitally from uncalibrated digital outputs. In a prototype 12-b fully differential two-step ADC implemented using a 2- mu m n-well CMOS technology, this technique cancels MOS switch feedthrough, op-amp offsets, and interstage gain errors simultaneously, and improves total harmonic distortion from -64 to -77 dB. >read more
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Proceedings ArticleDOI
High-level Accurate Model of High-resolution Pipelined ADC's
TL;DR: An accurate model for the systematic design and the simulation of high-resolution pipelined ADCs based on the non-linearities affecting the ADC whereas the goal is the evaluation of the best architecture matching the specifications.
Proceedings ArticleDOI
Efficient nyquist rate pipelined quantizer reliably yielding spurious free dynamic range beyond 100 db
Zheming Li,A.A. Abidi +1 more
TL;DR: Monte Carlo simulations in MATLAB indicate that the proposed architecture can guarantee over IO0 dB SFDR performance, even in the presence of large component non-ideality.
Proceedings ArticleDOI
CMOS pipelined A/D converters with concurrent error detection capability
TL;DR: A practical implementation of the design-for-testability (DfT) technique for self-calibrated, self-corrected pipelined analog-to-digital converters (ADCs) aimed at detecting ADC malfunctions during normal operation, but since it also enhances the observability in the converter, it can facilitate off-line testing as well.
Journal ArticleDOI
On the monotonicity and linearity of ideal radix-based A/D converters
János Márkus,István Kollár +1 more
TL;DR: In this paper, it is shown that these radix-based converters have nonmonotonic output and finite linearity.
Proceedings ArticleDOI
SCALES - A behavioral simulator for pipelined analog-to-digital converter design
TL;DR: This paper presents a Pipeline ADC simulator tool (SCALES) which allows topology selection and digital calibration of the frontend blocks and was developed in Python to allow platform independence in today's computer systems.
References
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Book
Probability, random variables and stochastic processes
TL;DR: This chapter discusses the concept of a Random Variable, the meaning of Probability, and the axioms of probability in terms of Markov Chains and Queueing Theory.
Book
Probability, random variables, and stochastic processes
TL;DR: In this paper, the meaning of probability and random variables are discussed, as well as the axioms of probability, and the concept of a random variable and repeated trials are discussed.
Journal ArticleDOI
A 10-b 20-Msample/s analog-to-digital converter
TL;DR: In this paper, a 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-mu m CMOS technology is described, which uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a SNDR of 60 dB with a full-scale sinusoidal input at 5 MHz.
Journal ArticleDOI
Full-speed testing of A/D converters
TL;DR: Improved computer-aided analog-to-digital converter (ADC) characterization methods based on the code density test and spectral analysis using the fast Fourier transform are described.
Journal ArticleDOI
A pipelined 5-Msample/s 9-bit analog-to-digital converter
Stephen H. Lewis,Paul R. Gray +1 more
TL;DR: A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology.
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