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Journal ArticleDOI

Digital-domain calibration of multistep analog-to-digital converters

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TLDR
A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs).
Abstract
A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs). While conventional self-calibration techniques require separate digital-to-analog converters (DACs) for calibration purpose to subtract nonlinearity errors in the analog domain, the proposed digital calibration technique uses add-on digital logic to subtract nonlinearity errors digitally from uncalibrated digital outputs. In a prototype 12-b fully differential two-step ADC implemented using a 2- mu m n-well CMOS technology, this technique cancels MOS switch feedthrough, op-amp offsets, and interstage gain errors simultaneously, and improves total harmonic distortion from -64 to -77 dB. >

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Proceedings ArticleDOI

Foreground digital calibration of non-linear errors in pipelined A/D converters

TL;DR: A foreground digital calibration technique for pipelined ADC is proposed which accounts for linear error correction, while an error estimation technique for amplifier non- linearity is suggested as a reference for non-linear error correction.
Reference EntryDOI

Digital‐To‐Analog Conversion

TL;DR: The sections in this article are Fundamentals of D/A Conversion, DAC Architectures, High-Resolution Techniques, Interpolative Oversampling Technique, and DAC Applications.
Journal ArticleDOI

Comments on "Comments on "Interstage gain-proration technique for digital-domain multistep ADC calibration

TL;DR: It is shown that the interstage gain error critically affects ADC linearities, even if there is no other error including digital truncation errors except the interStage gain error.
Journal ArticleDOI

A comparator-based cyclic analog-to-digital converter with multi-level input tracking boosted preset voltage

TL;DR: The CBSC is used to compensate for technology scaling and to reduce the power consumption of a 2.8 MS/s 10-bit cyclic analog-to-digital converter (ADC) using a multi-level input tracking preset voltage scheme.
References
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Book

Probability, random variables and stochastic processes

TL;DR: This chapter discusses the concept of a Random Variable, the meaning of Probability, and the axioms of probability in terms of Markov Chains and Queueing Theory.
Book

Probability, random variables, and stochastic processes

TL;DR: In this paper, the meaning of probability and random variables are discussed, as well as the axioms of probability, and the concept of a random variable and repeated trials are discussed.
Journal ArticleDOI

A 10-b 20-Msample/s analog-to-digital converter

TL;DR: In this paper, a 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-mu m CMOS technology is described, which uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a SNDR of 60 dB with a full-scale sinusoidal input at 5 MHz.
Journal ArticleDOI

Full-speed testing of A/D converters

TL;DR: Improved computer-aided analog-to-digital converter (ADC) characterization methods based on the code density test and spectral analysis using the fast Fourier transform are described.
Journal ArticleDOI

A pipelined 5-Msample/s 9-bit analog-to-digital converter

TL;DR: A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology.
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