Journal ArticleDOI
Digital-domain calibration of multistep analog-to-digital converters
S.-H. Lee,B.-S. Song +1 more
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TLDR
A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs).Abstract:
A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs). While conventional self-calibration techniques require separate digital-to-analog converters (DACs) for calibration purpose to subtract nonlinearity errors in the analog domain, the proposed digital calibration technique uses add-on digital logic to subtract nonlinearity errors digitally from uncalibrated digital outputs. In a prototype 12-b fully differential two-step ADC implemented using a 2- mu m n-well CMOS technology, this technique cancels MOS switch feedthrough, op-amp offsets, and interstage gain errors simultaneously, and improves total harmonic distortion from -64 to -77 dB. >read more
Citations
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Journal ArticleDOI
Design techniques for a low-power low-cost CMOS A/D converter
Dong-Young Chang,Seung-Hoon Lee +1 more
TL;DR: In this paper, a 10-bit algorithmic analog-to-digital converter (ADC) was designed to demonstrate design techniques for low-power low-cost CMOS integrated systems.
Patent
Method and system for calibrating analog-to-digital conversion
TL;DR: In this article, a reconstruction table (So,...,SM-1) is created that approximates the analog input signal in the digital domain using the knowledge of the analog signal waveform type.
Journal ArticleDOI
A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802.11b/Bluetooth receiver
TL;DR: A configurable time-interleaved pipeline architecture is presented as an efficient solution for the ADC design in high data rate multi-standard radios and its structure can be configured to accommodate the different sampling rate and dynamic range requirements of both standards.
Proceedings ArticleDOI
An Over-60dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp with 30dB Loop Gain
B.R. Gregoire,Un-Ku Moon +1 more
TL;DR: This work introduces correlated level shifting (CLS) that simultaneously decreases the error due to finite opamp gain and allows true rail-to-rail operation and there is no speed penalty when compared to a high-gain opamp solution.
Patent
Multi-stage high-performance amplifier
TL;DR: In this article, a two-stage switched-capacitor CMOS Miller-compensated amplifier uses only n-channel transistors in its signal path to reduce the deleterious effects of parasitic capacitances in the signal path.
References
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Book
Probability, random variables and stochastic processes
TL;DR: This chapter discusses the concept of a Random Variable, the meaning of Probability, and the axioms of probability in terms of Markov Chains and Queueing Theory.
Book
Probability, random variables, and stochastic processes
TL;DR: In this paper, the meaning of probability and random variables are discussed, as well as the axioms of probability, and the concept of a random variable and repeated trials are discussed.
Journal ArticleDOI
A 10-b 20-Msample/s analog-to-digital converter
TL;DR: In this paper, a 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-mu m CMOS technology is described, which uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a SNDR of 60 dB with a full-scale sinusoidal input at 5 MHz.
Journal ArticleDOI
Full-speed testing of A/D converters
TL;DR: Improved computer-aided analog-to-digital converter (ADC) characterization methods based on the code density test and spectral analysis using the fast Fourier transform are described.
Journal ArticleDOI
A pipelined 5-Msample/s 9-bit analog-to-digital converter
Stephen H. Lewis,Paul R. Gray +1 more
TL;DR: A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology.
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