Journal ArticleDOI
Dynamic depletion mode: an E/D MOSFET circuit method for improved performance
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TLDR
A new method of designing enhancement/depletion (E/D) MOSFET circuits, involving the dynamic or pulsed use of depletion-mode devices, is described, which can result in improvements in performance and/or power in the design of memory, logic, and driver circuits.Abstract:
A new method of designing enhancement/depletion (E/D) MOSFET circuits, involving the dynamic or pulsed use of depletion-mode devices, is described. The method can result in improvements in performance and/or power in the design of memory, logic, and driver circuits. The method is compared with the standard approach to the design of E/D circuits. Several circuits designed by the method have been simulated by use of a numerical circuit analysis program and have been placed on an experimental test chip. Theoretical and experimental results are presented.read more
Citations
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Journal ArticleDOI
VLSI circuit reconstruction from mask topology
N.P. van der Meijs,J.T. Fokkema +1 more
TL;DR: Attention is paid to fabrication tolerances, wire capacitance, wire resistance, coupling capacitances and capacitance associated with contacts and the aspect ratio of (non-rectangular) transistors.
Book
Analog-to-Digital Conversion
TL;DR: Analog-to-Digital Conversion presents an overview of the state-of-the-art in this field and focuses on issues of optimizing accuracy and speed while reducing the power level, which makes it a reference for the experienced engineer.
Patent
Tri-state output buffer circuit including a capacitor and dynamic depletion mode switching device
TL;DR: In this paper, a tri-state output buffer is provided which incorporates a dynamic depletion mode circuit, which acts to rapidly transfer the charge from the capacitor to the gate of the pull-up transistor.
Patent
CMOS/NMOS integrated circuit with supply voltage delay variation compensation
TL;DR: In this article, the authors proposed a ring oscillator, which consists of two blocks of inverters connected in series, and the output of the first block is connected to the input of the second block.
Journal ArticleDOI
Simple analytical models for the temperature dependent threshold behavior of depletion-mode devices
Richard C. Jaeger,F.H. Gaensslen +1 more
TL;DR: In this paper, the relationship between threshold voltage shift and implanted donor dose and position is extended to include impurity freezeout at low temperatures, and a simple model for the observed low substrate sensitivity at low temperature is presented.
References
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An algorithm for dc solutions in an experimental general purpose interactive circuit design program
TL;DR: In this paper, an algorithm for computing dc solutions for electronic circuits is presented, which is shown to be reliable and efficient for practical circuits which include bipolar, FET, and Josephson junction circuits.
Proceedings ArticleDOI
Design of short-channel ion-implanted mosfets with relatively deep junctions
TL;DR: In this article, a short-channel ion-implanted MOSFET with relatively deep junctions is considered and four device parameters are considered: threshold and transconductance reduction, sub-threshold turn-on, and punch-through.
Patent
Method for producing improved transistor devices
TL;DR: In this article, the problem of aligning the gate electrode over the channel region, lying between the source region and the drain region of a field effect transistor, is particularly addressed and solved.
Proceedings ArticleDOI
Threshold adjustment of N-channel enhancement mode FETs by ion implantation
P. P. Peressini,W.S. Johnson +1 more
TL;DR: In this paper, the threshold voltage of n-channel enhancement mode FETs was determined as a function of implant dose and energy by measuring the difference in threshold voltage between implanted and unimplanted devices on the same wafer.
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