Durham Research Online
Deposited in DRO:
27 April 2016
Version of attached le:
Accepted Version
Peer-review status of attached le:
Peer-reviewed
Citation for published item:
Shahbazi, M. and Poure, P. and Saadate, S. and Zolghadri, M.R. (2013) 'FPGA-based fast detection with
reduced sensor count for a fault-tolerant three-phase converter.', IEEE transactions on industrial informatics.,
9 (3). pp. 1343-1350.
Further information on publisher's website:
http://dx.doi.org/10.1109/TII.2012.2209665
Publisher's copyright statement:
c
2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in
any current or future media, including reprinting/republishing this material for advertising or promotional purposes,
creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of
this work in other works.
Additional information:
Use policy
The full-text may be used and/or reproduced, and given to third parties in any format or medium, without prior permission or charge, for
personal research or study, educational, or not-for-prot purposes provided that:
•
a full bibliographic reference is made to the original source
•
a link is made to the metadata record in DRO
•
the full-text is not changed in any way
The full-text must not be sold in any format or medium without the formal permission of the copyright holders.
Please consult the full DRO policy for further details.
Durham University Library, Stockton Road, Durham DH1 3LY, United Kingdom
Tel : +44 (0)191 334 3042 | Fax : +44 (0)191 334 2971
https://dro.dur.ac.uk
Abstract— Fast fault detection and reconfiguration is
necessary for fault tolerant power electronic converters in safety
critical applications to prevent further damage and to make the
continuity of service possible. The aim of this study is to minimize
the number of the used additional voltage sensors in a fault
tolerant three-phase converter. In this paper, first a practical
implementation of a very fast fault detection scheme with
reduced sensor number is discussed. Then, an optimization in
this scheme is also presented to decrease the detection time. For
fault detection, special time and voltage criterion are applied to
observe the error in the estimated phase-to-phase voltages for a
specific period of time. The proposed optimization is based on the
fact that following a detectable fault, two line to line voltages will
deviate from their respective estimated values.
Fault detection is studied for a three-leg two-level fault
tolerant converter. Control and fault detection systems are
implemented on a single FPGA. First, Hardware In the Loop
experiments are carried out to evaluate the implemented
schemes. Then, fully experimental tests are performed. The
results confirm good performance of the proposed detection
schemes, the digital controller and the fault tolerant structure. It
is shown that such methods can detect and locate a fault in a few
tens of microseconds. In certain cases the optimized scheme can
be faster up to 50%, and in the other cases they have the same
detection time.
Index Terms— Fault detection, Fault tolerant converter, Field-
Programmable Gate Array (FPGA), Hardware In the Loop
(HIL).
I. I
NTRODUCTION
OWER electronic converters are widely used in a variety
of applications, especially in three phase systems as
Manuscript received October 24, 2011. Accepted for publication Mars 14,
2012.
Copyright © 2009 IEEE. Personal use of this material is permitted. However,
permission to use this material for any other purposes must be obtained from
the IEEE by sending a request to pubs-permissions@ieee.org
M. Shahbazi is with the Sharif University of Technology, Tehran, Iran and
the Université de Lorraine, Nancy, France (email: Mahmoud.Shahbazi@
green.uhp-nancy.fr).
M. R. Zolghadri is with the Sharif University of Technology, Tehran, Iran
(email: zolghadr@sharif.edu)
P. Poure and S. Saadate are with the Université de Lorraine, Nancy, France
(phone: +33-383684160; e-mail: Philippe.Poure@lien.uhp-nancy.fr;
Shahrokh.Saadate@green.uhp-nancy.fr).
rectifiers or inverters. However, they are very sensitive to
failure in one of their semiconductor switches. A sudden
failure in one switch of a power electronic converter will
decrease the performance of the system and may even lead to
a hard failure. For this reason, fault tolerant converters have
been an interesting topic of research in recent years [1-6].
Using a fault tolerant converter increases the reliability and
availability of the system. To reduce the failure rate and to
prevent unscheduled shutdown, real-time fault detection,
isolation, and compensation schemes are necessary. This is
especially essential for safety critical operations such as in
military and aerospace applications.
In order to make suitable response to a fault in one of the
semiconductor devices, the first step is to perform fast fault
detection and to find the fault’s location. Several papers have
discussed fault detection schemes. A detection method for
faults in IGBT switches based on gate signal monitoring is
presented in [6]. In [7], Fault is detected in a cascaded
multilevel converter by comparing the generated AC-side
output voltage with its reference. Average values of three-
phase currents are processed in [8] to detect an open switch
fault in a doubly-fed wind power converter. Open-circuit fault
detection in matrix converters is done in [9] by monitoring the
modulated voltage errors of the bidirectional switches.
Nonlinear observers are used in [10] to detect open-switch
faults in induction motor drives. Another method for detection
of open-switch faults in voltage source inverters feeding AC
drives based on analyzing the load currents is presented in
[11]. Fast detection schemes are proposed in [12, 13], which
are based on a “time and voltage criterion” and can detect and
locate a fault in a few tens of microseconds.
Although fast,
these methods use one voltage sensor for each leg to detect the
fault. A large number of sensors may decrease reliability and
add additional costs. In this paper it is shown that this number
can be reduced and in fact it is effectively possible to use only
two voltage sensors for fast fault detection in a conventional
three-leg converter. Here, first an effective method is proposed
for fault detection with only two additional voltage sensors.
Although fast and simple, in some rare cases this method
might be up to two times slower than the methods presented in
[12, 13]. Therefore an optimization is presented to solve this
problem. The proposed method and the optimized version use
two line to line voltages at the output of the three-leg
FPGA-based Fast Detection with Reduced
Sensor Count for a Fault-Tolerant Three-Phase
Converter
Mahmoud Shahbazi, Philippe Poure
,
Member,
IEEE
,
Shahrokh Saadate
,
and MohammadReza
Zolghadri, Member, IEEE
P
converter and use specific voltage and time criterions to detect
the fault location. The proposed optimization is based on the
fact that following a detectable fault, two line to line voltages
will deviate from their respective estimated values. In order to
perform very fast fault detection, the algorithm must be
implemented on a very fast digital target. Thanks to its parallel
architecture, FPGA can run the tasks very quickly; as a result,
it appears to be the most suitable choice for implementation of
this type of fault detection schemes. Besides, the high
performance of FPGA in many power electronic and drive
applications has been proved [14, 15]. By implementing both
fault detection and converter control units on a single FPGA
chip, cost will be decreased. Therefore, in this paper, a FPGA
is used to perform both these tasks. The FPGA
implementation procedure is based on a methodology for rapid
prototyping, developed in our laboratory [16]. Hardware In the
Loop (HIL) and then fully experimental tests are carried out to
validate the effectiveness of this system. More, in order to
achieve continuity of service after the fault detection, it is
necessary to change the converter topology as well. Several
schemes are proposed as fault tolerant topologies for power
converters [1]. In this paper, a scheme with an extra leg
presented in [12] is studied, mainly to verify the effectiveness
of the proposed fault detection method. However the study of
the fault tolerant topologies is out of the scope of this paper. It
should be noted that the proposed fault detection methods are
applicable to any other form of three-phase two-level fault
tolerant converter as well.
In the following, first in part II the fault tolerant topology,
the proposed fault detection method and also its optimized
scheme are presented. Then, FPGA implementation for
Hardware In the Loop (HIL) verification is explained and the
HIL results are presented in part III. The fully experimental
results are provided in part IV. The presented results show the
effectiveness of the proposed fault detection and
reconfiguration schemes. Also it is shown that the proposed
optimization can make the fault detection process faster in
some cases.
II. T
HE FAULT TOLERANT CONVERTER
A. Converter Topology
The studied fault tolerant converter is shown in Fig. 1. It is
studied in [12] for an active filter application. Before the fault
occurrence in one of the semiconductor switches, all three
TRIACs are turned off and the fault tolerant converter
operates like a conventional one. After the fault detection, the
commands of the switches of the faulty leg are removed and
by triggering the suited TRIAC, the extra leg will replace the
faulty one. The commands of the faulty leg will then be
applied to this extra leg.
B. Fault detection with reduced sensor number
Very fast fault detection is possible using the
aforementioned approach of [12, 13]. By using this method, 3
extra voltage sensors are needed to measure the voltage of
each phase in respect to the DC middle point “n” (so called
“pole voltages”), as depicted in Fig.2-a. In fact, this number
can be reduced for fault detection in three leg converter. The
hardware structure and the placement of the voltage sensors in
this case are shown in Fig.2-b. Note that in Fig. 2 only the
three main legs of the converter are shown. The redundant leg
is not shown, because before the fault detection it is
disconnected from the AC side and is not switched. The two
measured voltages in Fig. 2-b are named as
and
,
and the third line to line voltage
may be calculated
using these two values.
Fig. 3 shows the principle of the proposed detection
method. A fault is detected based on the difference between
measured and estimated voltages. It is worth mentioning that
although only open circuit fault is discussed here, short circuit
fault in IGBTs can be detected as well by using fast acting
fuses in series with each IGBT. In fact, in this protection
scheme, a short circuit fault will finally result in an open
circuit condition, as it is explained and experimentally
approved in [17]. Therefore the fault can be effectively
detected [12]. On the other hand, in our detection approach the
IGBT’s failure is realized for the set of “driver+switch”.
Therefore once a fault in a driver or in a switch is occurred,
the “driver+switch” cannot perform the desired action, and the
fault must be detected. Since the effect is the same for fault
detection, nothing differentiates the failure in driver from that
in the switch. Therefore a fault in the driver will be detected as
well.
Estimated voltages are calculated based on the switch
commands and the DC-link voltage as given below:
(1)
(2)
(3)
while
,
,
∈
0,1
are the commands for the upper
switch of each leg.
0 indicates that the switch is
Fig. 1. Fault tolerant converter topology.
Fig. 2.
Placement of the voltage sensors for (a) pole voltage measurement
(b) leg-leg voltage measurement.
commanded to be open, whilst
1 means that the switch is
commanded to be closed. The switch commands in each leg
are complementary.
As a result of non-ideal behavior of power switches, delays
and dead times are inevitable. Also, there will be measurement
and discretizing errors. Therefore, even in normal operation of
the converter, the estimated and measured voltages are not
always the same. Hence two adjustments are used: a
comparator is used to determine if the difference between
measured and estimated voltage is large enough to be
considered as an error and a time criterion is also employed to
compensate for delays and dead times in the converter. In Fig.
3, the three Fault Detection (FD) subsystems named FD12,
FD23 and FD31 check the three line to line voltages. The
outputs of these three fault detection blocks are sent to the
“fault identification” block which determines the exact fault
location.
The FD12 subsystem’s details are shown in Fig. 4. FD23
and FD31 operate in a similar way. Here the error signal is
observed, and if it is always greater than a threshold value (h)
for a long enough time (N observation periods), then it may be
concluded that there is a fault. This observation time should be
longer than the overall delays caused by the sensors, drivers,
controller and switches; otherwise the inherent delay of the
system may be interpreted as a fault. Fig. 5 shows the state
machine which is used as the “fault identification” block and
finds the fault location based on the outputs from the three FD
blocks. It is obvious that fault in any leg affects the two
measured line to line voltages between the faulty leg and each
healthy leg. Therefore, after each fault, two detection units
will detect the occurrence of a fault. These two signals can be
used to locate the fault. For example, a fault in the leg 2 will
result in deviation of the
and
from their respective
estimated values, therefore fault detection blocks FD12 and
FD23 will detect this faulty condition. Using this information,
it is possible to detect that the fault has been actually occurred
in leg 2.
There is some particular cases compared to conventional
schemes with 3 sensors that should be taken care of. It should
be noted that in these cases, detection of a fault in one leg
might be perturbed and delayed because of a changing
switching command in one of the other legs. For example, let
us consider that
IGBT is faulty and instead of that, diode
is conducting.
is also switched on. The output of the up-
counter in FD12 starts to increase, but if the command of the
leg 2 changes before the fault detection, the error between the
measured and estimated values of
will be momentarily
almost equal to zero and a reset signal will be applied to the
counter. Although the probability of this occurring is low, its
effect increases the detection time to two times. It should be
noted that in the mentioned cases, the fault is still detectable,
only the fault detection is slower in comparison with the
schemes with three voltage sensors [12, 13].
In order to preserve the desired detection speed (detection in
N samplings), an optimization is proposed in the following
section.
C. Optimized fault detection with reduced number of
sensors
The idea behind this optimization comes from the fact that
in the aforementioned situation, although the switching in
another leg will reduce the error between the measured and
estimated voltages of those two legs to zero, in the same time
it produces an error in the voltage between the switched leg
and the third leg. In other words, when there is a detectable
fault in the converter, two out of three measured voltages are
different from their respective estimated ones, and two
counters of fault detection units operate.
The optimized fault detection scheme is shown in Fig. 6.
The two measured and the third calculated line to line voltages
and also the control signals and the measured DC-link voltage
are sent to the detection unit. The detection unit consists of
two subsystems, for detection of the fault and its location. The
principle of fault detection subsystem is detailed in Fig. 7. All
three corresponding estimated and measured (or calculated)
Fig. 3. Fault detection and identification with two voltage sensors.
Fig. 4. Detection of a fault (Block FD12).
Fig. 5. State diagram of the “fault identification” block.
voltages are compared, and if there is a large enough error in
at least two of the line to line voltages, the counter operates,
otherwise the counter will be reset to zero. If the counter
output is larger than a constant “N”, the fault is declared. Note
that in this case, in contrary to the non-optimized scheme
(Figs. 3 to 5), a switching in a healthy leg cannot interrupt the
detection process, because the output of the summation block
in Fig. 7 will remain equal to 2 after the switching. When the
fault is detected, it is necessary to detect its location as well.
After a fault, the line to line voltage of the two healthy legs
has the minimum anomaly; therefore the 2
nd
subsystem tries to
find the line to line voltage with minimum error during the
fault detection. This is carried out by using simple units for
counting the activity over last N samplings and a state
machine, as shown in Fig. 8. For example, when a fault is
detected and the Error31 signal has minimum activity over the
last N samplings in comparison with Error12 and Error23, it
can be concluded that both legs “3” and “1” are healthy, and
therefore the error is in leg “2”.
III. FPGA
I
N THE
L
OOP VALIDATION
Designing and testing digital control systems for power
electronics applications can be expensive and time consuming.
More, traditional simulations cannot exactly reproduce the real
condition, because they do not take into account some
limitations of real controllers, like the limited resolution of
registers or saturation of values in fixed point systems during
the intermediate steps of calculations. Also the fully
experimental tests may not be always possible or may be
potentially damaging, particularly in fault condition tests. One
interesting solution to eliminate the risk of damaging the real
plant while testing the digital controller in a realistic manner is
Hardware-in-the-loop (HIL) analysis [12, 16].
In order to verify the effectiveness of the proposed detection
scheme, the optimized one and also the control parts, the
detection and control systems are implemented on a FPGA.
The FPGA can execute its tasks quasi-instantaneously. This
characteristic is very useful for fault detection schemes. For
this experiment, a Stratix DSP S80 development board is used,
which includes the Stratix EP1S80B956C6 FPGA chip. In
order to carry out the FPGA implementation for HIL
experiments, a top-down design flow is used, as shown in Fig.
9. The flow consists of four parts: fundamental simulations,
mixed simulation, HIL and finally fully experimental test.
Fig. 6. Fault detection and identification in the optimized scheme.
Fig. 7. Detection of fault occurrence in the optimized scheme.
Fig. 8. Detection of fault location in the optimized scheme.
