Proceedings ArticleDOI
Heterogeneous 3D integration — Technology enabler toward future super-chip
Mitsumasa Koyanagi
- pp 6724539
TLDR
In this paper, a new concept of heterogeneous 3D integration called a super-chip is introduced, in which various kinds of device chips with different size, different devices and different materials are stacked.Abstract:
To overcome various concerns caused by scaling-down the device size, it is indispensable to introduce a new concept of heterogeneous 3D integration called a super-chip in which various kinds of device chips with different size, different devices and different materials are stacked. A key technology of self-assembly and electrostatic (SAE) temporary bonding has been developed to achieve a super-chip. Several kinds of super-chips are fabricated by stacking compound semiconductor device chip, photonic device chip and spintronic device chip on CMOS device chips.read more
Citations
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Journal ArticleDOI
A mmWave Folded Substrate Integrated Waveguide in a 130-nm CMOS Process
TL;DR: In this paper, a miniaturized millimeter-wave substrate integrated waveguide (SIW) in IBM 130-nm digital CMOS process is presented in order to reduce the footprint of the interconnect compared with previous works using the folding technique.
Journal ArticleDOI
Electrical Characterization of Coaxial Silicon–Insulator–Silicon Through-Silicon Vias: Theoretical Analysis and Experiments
TL;DR: In this paper, a fabrication friendly coaxial TSV configuration based on heavily doped silicon-insulator-silicon (SIS) structure, whose electrical characteristics are studied through deriving analytical solution, performing numerical simulation, and conducting experimental measurement.
Journal ArticleDOI
Wideband Capacitance Evaluation of Silicon–Insulator–Silicon Through-Silicon-Vias for 3D Integration Applications
TL;DR: In this article, a silicon-insulator-silicon through silicon-via (TSV) using ultra-low-resistivity silicon pillar as the conductor, while polymer benzocyclobutene as an insulation layer was successfully fabricated.
Journal ArticleDOI
Recent progress in 3D integration technology
TL;DR: 3D integration technology is the key for future LSIs with highperformance, low-power and multi-functionality, and it is indispensable to introduce a new concept of heterogeneous 3D integration in which various kinds of materials, devices and technologies are integrated on a Si substrate.
Journal ArticleDOI
Development of Eccentric Spin Coating of Polymer Liner for Low-Temperature TSV Technology With Ultra-Fine Diameter
TL;DR: In this article, a low-cost and low-temperature process involving spin coating of polyimide liner, electroless plating of Ni barrier/seed layer, and electroplating of Cu, which is suitable for via-middle/via-last processes that have a more stringent thermal budget.
References
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Journal ArticleDOI
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
Uk-Song Kang,Hoe-ju Chung,Seongmoo Heo,Soon-Hong Ahn,Hoon Lee,Sooho Cha,Jaesung Ahn,Duk-Min Kwon,Jin-Ho Kim,Jae-Wook Lee,Han-Sung Joo,Woo-Seop Kim,Hyun-Kyung Kim,Eun-Mi Lee,So-Ra Kim,Keum-Hee Ma,Dong-Hyun Jang,Nam-Seog Kim,Man-Sik Choi,Sae-Jang Oh,Jung-Bae Lee,Tae-Kyung Jung,Jei-Hwan Yoo,Chang-Hyun Kim +23 more
TL;DR: An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules and the proposed TSV check and repair scheme can increase the assembly yield up to 98%.
Proceedings ArticleDOI
Hybrid memory cube new DRAM architecture increases density and performance
Joe M. Jeddeloh,Brent Keeth +1 more
TL;DR: The Hybrid Memory Cube is a three-dimensional DRAM architecture that improves latency, bandwidth, power and density and Heterogeneous die are stacked with significantly more connections, thereby reducing the distance signals travel.
Proceedings ArticleDOI
Testing 3D chips containing through-silicon vias
TL;DR: This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges, and discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wader-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.
Journal ArticleDOI
High-Density Through Silicon Vias for 3-D LSIs
TL;DR: The 3-D microprocessor test chip,3-D memorytest chip, 3- D image sensor chip, and 3-Ds artificial retina chip were successfully fabricated by using poly-Si TSV and tungsten (W/poly-Si) TSV technology.
High-Density Through Silicon Vias for 3-D LSIs : Silicon stacked chips that perform highly-parallel data transfer have been successfully fabricated for image processing, artificial retinas, and for microprocessor and memory testing
TL;DR: In this paper, a polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly poly-Si TSV for 3D integration was developed.