Proceedings ArticleDOI
High-k gate dielectrics for scaled CMOS technology
Tso-Ping Ma
- Vol. 1, pp 297-302
Reads0
Chats0
TLDR
In this paper, several high-k gate dielectrics, including TiO/sub 2, Ta/sub2, O/sub 5, ZrO/ sub 2, HfO sub 2, and Al-doped versions of the above, have been studied.Abstract:
This paper summarizes our results on several high-k gate dielectrics, including TiO/sub 2/, Ta/sub 2/O/sub 5/, ZrO/sub 2/, HfO/sub 2/, and Al-doped varieties of the above. Among them, TiO/sub 2/ and Ta/sub 2/O/sub 5/ have higher dielectric constants than others, while ZrO/sub 2/ and HfO/sub 2/ are thermodynamically more stable against the formation of SiO/sub 2/ on Si, and the addition of Al raises the temperature for crystallization for all of them. Both MOS capacitors and MOSFET's have been fabricated with these high-k gate dielectrics, and their properties have been studied. We have also utilized the temperature-dependent IN characteristics of these high-k dielectrics to study their current conduction mechanisms and to construct their energy band diagrams.read more
Citations
More filters
Journal ArticleDOI
Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks
Bigang Min,Siva Prasad Devireddy,Zeynep Celik-Butler,Fang Wang,Anna Zlotnicka,Hsing-Huang Tseng,Philip J. Tobin +6 more
TL;DR: In this paper, low-frequency noise measurements were performed on p-and n-channel MOSFETs with HfO/sub 2/23/spl Aring/ and HfAlO/ sub x/ 28.5/spl Ring/, and double-gate oxide structures where an interfacial oxide layer of 40 /spl RING/ was grown between the high/spl kappa/ dielectric and Si.
Journal ArticleDOI
Physics-based 1/ f noise model for MOSFETs with nitrided high- κ gate dielectrics
Tanvir Morshed,Siva Prasad Devireddy,Zeynep Celik-Butler,A. Shanware,Keith Green,James J. Chambers,Mark R. Visokay,Luigi Colombo +7 more
TL;DR: In this paper, a physics-based low frequency noise model was developed for MOSFET devices with nitrided high- κ gate dielectric materials, which is built upon the correlated carrier number and surface mobility fluctuations theory, where the original Unified Model was modified to take into account the multilayered structure of the high- ǫ gate dieetics, and the resultant charge carrier tunneling process in terms of a two-step cascaded barrier instead of a single step barrier.
Journal ArticleDOI
High-k Al/sub 2/O/sub 3/ gate dielectrics prepared by oxidation of aluminum film in nitric acid followed by high-temperature annealing
TL;DR: In this article, an aluminum oxide gate dielectric was prepared by oxidation of ultrathin Al film in nitric acid (HNO/sub 3/) at room temperature then followed by high-temperature annealing in O/sub 2/ or N/Sub 2/.
Journal ArticleDOI
Low-frequency noise in TaSiN/HfO/sub 2/ nMOSFETs and the effect of stress-relieved preoxide interfacial layer
Siva Prasad Devireddy,Bigang Min,Zeynep Celik-Butler,Hsing-Huang Tseng,Philip J. Tobin,Fang Wang,Ania Zlotnicka +6 more
TL;DR: In this paper, low-frequency noise characteristics are reported for TaSiN-gated n-channel MOSFETs with atomic-layer deposited HfO/sub 2/ on thermal SiO/ sub 2/ with stress-relieved preoxide (SRPO) pretreatment.
Journal ArticleDOI
A low-frequency noise model for advanced gate-stack MOSFETs
TL;DR: The proposed multi-stack unified noise (MSUN) model is based on number and correlated mobility fluctuations theory developed for native oxide MOSFETs, and offers scalability with respect to the high- k /interfacial layer thicknesses.
References
More filters
Journal ArticleDOI
Making silicon nitride film a viable gate dielectric
TL;DR: In this article, high-quality silicon nitride (or oxynitride) films made by a novel jet vapor deposition (JVD) technique are described, which utilizes a high-speed jet of light carrier gas to transport the depositing species onto the substrate to form the desired films.
Journal ArticleDOI
1.5 nm direct-tunneling gate oxide Si MOSFET's
Hiroki Sasaki,Mizuki Ono,Takashi Yoshitomi,Tatsuya Ohguro,S. Nakamura,Masanobu Saito,Hiroshi Iwai +6 more
TL;DR: In this paper, a 1.5 nm direct-tunneling gate oxide was used to achieve a transconductance of more than 1,000 mS/mm at a gate length of 0.09 /spl mu/m at room temperature.
High Quality Ultra-thin TiOJSi3N4 Gate Dielectric for Giga Scale MOS Technology
Xin Guo,T. Tamagawa +1 more
TL;DR: In this article, physical and electrical properties of ultra-thin (2.0-3.0 nm EOT) Ti02/Si3N4 stack gate dielectrics for future giga scale MOS technology were studied.
Related Papers (5)
High-k Gate Dielectrics of Thin Films with its Technological Applications -A Review
B. Rajesh Kumar,T. Subba Rao +1 more