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Faculty Publications from the Department of
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3-2011
High Power Current Sensorless Bidirectional 16-Phase Interleaved High Power Current Sensorless Bidirectional 16-Phase Interleaved
DC-DC Converter for Hybrid Vehicle Application DC-DC Converter for Hybrid Vehicle Application
Liqin Ni
University of Nebraska-Lincoln
, liqin.ni@huskers.unl.edu
Dean J. Patterson
University of Nebraska-Lincoln
, patterson@ieee.org
Jerry L. Hudgins
University of Nebraska-Lincoln
, jhudgins2@unl.edu
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Ni, Liqin; Patterson, Dean J.; and Hudgins, Jerry L., "High Power Current Sensorless Bidirectional 16-Phase
Interleaved DC-DC Converter for Hybrid Vehicle Application" (2011).
Faculty Publications from the
Department of Electrical and Computer Engineering
. 182.
https://digitalcommons.unl.edu/electricalengineeringfacpub/182
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012 1141
High Power Current Sensorless Bidirectional
16-Phase Interleaved DC-DC Converter for
Hybrid Vehicle Application
Liqin Ni, Member, IEEE, Dean J. Patterson, Fellow, IEEE, and Jerry L. Hudgins, Fellow, IEEE
Abstract—A new 16-phase interleaved bidirectional dc/dc con-
verter is developed featuring smaller input/output filters, faster
dynamic response and lower device stress than conventional de-
signs, for hybrid vehicle applications. The converter is connected
between the ultracapacitor (UC) pack and the battery pack in a
multisource energy storage system of a hybrid vehicle. Typically,
multiphase interleaved converters require a current control loop in
each phase to avoid imbalanced current between phases. This in-
creases system cost and control complexity. In this paper, in order
to minimize imbalance currents and remove the current control
loop in each phase, the converter is designed to operate in discon-
tinuous conduction mode (DCM). The high current ripple associ-
ated with DCM operation is then alleviated by interleaving. The
design, construction, and testing of an experimental hardware pro-
totype is presented, with the test results included. Finally, a novel
soft switch topology for DCM operation is proposed for future re-
search, to achieve zero-voltage switching (ZVS), or zero-current
switching (ZCS) in all transitions.
Index Terms—Battery, discontinuous conduction mode, energy
storage system, multiphase interleaved dc-dc converter, PHEV hy-
brid electric vehicle, soft switching, ultracapacitor.
I. INTRODUCTION
T
HE TRANSITION from internal combustion engine (ICE)
vehicles to pure electric vehicles (EVs), or hybrid electric
vehicles (HEVs) is very attractive and desirable, but there are
still some serious issues with regard to energy storage technol-
ogy. The lithium-ion battery is the most commonly used energy
storage device in current hybrid vehicles, because of its high
power and energy density. However, it has over-heating issues,
limited life cycle, and durability limitations, especially under
high power conditions. In contrast, the ultracapacitor has the
advantages of a long life cycle, high output power and high re-
liability. Thus, the combination of batteries and ultracapacitors
as an energy storage unit is a potential solution to improving
vehicle performance, battery lifetime, and durability [1], [2].
It also offers excellent performance in both high acceleration
Manuscript received December 27, 2010; revised March 15, 2011, May 21,
2011, and July 12, 2011; accepted July 30, 2011. Date of current version
February 7, 2012. This project was supported by the Nebraska Center for Energy
Sciences Research and the Nebraska Public Power District. Recommended for
publication by Associate Editor V. Agarwal.
The authors are with the Department of Electrical Engineering, University
of Nebraska-Lincoln, 209N SEC P.O. Box 880511, Lincoln, NE 68588 USA
(e-mail: liqin.ni@huskers.unl.edu; patterson@ieee.org; jhudgins2@unl.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2011.2165297
Fig. 1. Typical topology of a battery and ultracapacitor energy storage system.
and regenerative braking. The typical topology of a battery and
ultracapacitor energy storage system is shown in Fig. 1. The
battery pack is parallel connected with the ultracapacitor pack
through a bidirectional dc/dc converter [3], [4]. One objective
of the design is that the converter has to achieve a high power
density with low current/voltage ripple, particularly on the bat-
tery side. Moreover, the converter has to meet basic automotive
industry requirements, such as high efficiency, low cost, low
EMI, and compact component size. Several different circuit de-
signs for high power applications have been published [5]–[10].
Most of these designs require large inductors/transformers and
devices with high voltage/current ratings. The volumes of these
components are generally large [7]–[10], or the designs have
the disadvantage of limited voltage ratio [5], [6]. A multiphase
interleaved dc/dc converter is adopted as a good solution for the
application with high power and high current with low current
ripple.
Interleaving techniques have been widely used in power con-
verters in recent years [9], [11]–[16]. Typical benefits of inter-
leaving techniques include reduced device stress by separating
power into each discrete phase, reduced filter size by increas-
ing effective frequency, and alleviation of the effects of current
ripple. The interleaving technique also enables other beneficial
technology changes, such as replacement of aluminum elec-
trolytic or polymer organic capacitors by film or ceramic capac-
itors, which improves the equivalent series resistance, power
density, and reliability in a rugged thermal environment.
However, most of the published papers require a current con-
trol loop in each phase to achieve balanced phase currents and
to improve dynamic response [13], [16]–[18]. The cost, weight,
and control complexity grows when the number of phases in-
creases, which limits the total number of phases to be consid-
ered. The optimum number of phases will be another issue that
has to be considered [12], [19], [20]. The imbalance current
0885-8993/$26.00 © 2011 IEEE
1142 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012
mainly depends on duty cycle differences, inductance value dif-
ferences, and parasitic resistance differences among different
phases, all of which integrate over time in a continuous conduc-
tion mode converter. In order to minimize imbalance currents
and eliminate current control loops, some authors designed a
synchronous converter working in continuous conduction mode
(CCM) [14], [15]. However, the inductor current falls to a neg-
ative value during every switching cycle, which would lead to a
higher current ripple per phase and lower efficiency, especially
for light load conditions.
This paper proposes the design of a 16-phase interleaved
power converter operating in discontinuous conduction mode
(DCM) that improves the current balance without using current
control loops, which can simplify control system and reduce
cost. This also allows the circuit to use a larger number of
phases, which decrease power stress on each device and reduce
filter size requirements. Therefore, compared to traditional dc/dc
converters with current control, the proposed method is a cost-
effective approach.
The design also features fast dynamic response since the
phase current is reset to zero at every switching cycle. To verify
the proposed approach, a 45-kW hardware prototype has been
constructed and tested with experimental results presented.
II. I
NTERLEAVING DC/DC CONVERTER IN DCM
A. Interleaved Converter Topology and Operation
The multiphase interleaved dc/dc converter is a circuit topol-
ogy where basic converter circuits are placed in parallel between
input and output. The number of phases is in relation to effi-
ciency, cost, volume, and control complexity. This paper adopts
16 phases based on a previous research [12]. Also, a 16 phase
design will result in moderate current flow in each phase. There-
fore, switches and filters will be smaller and easy to obtain/build.
The optimization of the number of phases is a critical issue and
will be further investigated in a separate paper. The schematic
diagram of the 16-phase interleaved dc/dc converter is shown in
Fig. 2. An ultracapacitor pack is placed on the low-voltage side
with voltage range 86.4 to 172.8 V, and a battery pack is placed
on the high-voltage side with a voltage range of 192 to 268.8 V.
The battery voltage working range in this paper is designed to
be compatible with 2004 Toyota Prius specifications. The high-
voltage side is also connected with the traction system or load.
When the demand power is larger than the battery pack rated
power, the ultracapacitor pack releases power for acceleration
and the converter operates in boost mode. When the ultraca-
pacitor pack is not fully charged and the regenerative braking
power is larger than the battery pack rated power, the ultraca-
pacitor pack absorbs power from regenerative braking and the
converter operates in buck mode.
The switch gate signals and inductor currents are shown in
Fig. 3. The gate signals for the phases are exactly shifted by
360
◦
/N (N is the number of phases, here N = 16). All phase
currents have the same waveform, except that they are shifted
360
◦
/N. The ripple in the low voltage side current i
L
, which is
the sum of all low side phase-currents, is significantly reduced
Fig. 2. Power stage of a 16-phase bidirectional DC/DC converter.
due to harmonic elimination. Furthermore, the frequency of the
ripple in i
L
is increased to N∗f
s
(f
s
is the switching frequency).
Because of lower current ripple and less harmonic content,
the size of the filter capacitance on the low voltage side can be
reduced, or even removed. The filter capacitance on the high
side is composed of N capacitors. Each one is placed physically
close to its phase, in order to reduce the parasitic inductance
between the switch and the capacitor. Each phase processes
only 1/N of the total power, which, therefore, reduces the stress
on the switching devices.
B. Synchronous DC/DC Converter in DCM
This proposed design is working in DCM so that the system
has a small imbalance current and fast response, since the induc-
tor current is reset to zero at every switching cycle. Moreover, the
inductance requirement for each phase is small in DCM. The
converter current is related with duty ratio directly in DCM,
which could simplify the control system.
In boost operation mode, the duty ratio of the main switch
(low side switch, e.g., Q1_1) is a function of output current, and
can be calculated by the following equation:
D
boost
=
2Lf
s
I
H
(V
H
− V
L
)
N · V
2
L
(1)
where L is the inductance in each phase, f
s
is the switch fre-
quency, I
H
is the average current on the high voltage side, V
H
is the voltage on the high voltage side, V
L
is the voltage on the
low voltage side, and N is the number of phases.
In a synchronous converter in CCM, the duty ratio D
of
the freewheeling MOSFET equals
¯
D with necessary dead time.
In DCM, the freewheeling MOSFET has to be turned
OFF by
zero current detection on the inductor current, or the on-time is
estimated by the control stage. In this paper, the on-time of the
freewheeling MOSFET is estimated by the following equation
in boost mode
D
boost
=
D
boost
· V
L
V
H
− V
L
. (2)
NI et al.: HIGH POWER CURRENT SENSORLESS BIDIRECTIONAL 16-PHASE INTERLEAVED DC-DC CONVERTER 1143
Fig. 3. Gate signals and inductor currents waveforms.
Fig. 4. D
estimation result in boost converter (see v
g 2
).
In buck operation mode, the duty ratio functions for the main
switch and freewheeling MOSFET are calculated by (3) and (4),
respectively
D
buck
=
2Lf
s
I
L
V
L
N · V
H
(V
H
− V
L
)
(3)
D
buck
=
D
buck
· (V
H
− V
L
)
V
L
. (4)
Figs. 4 and 5 show the results of D
estimation by (2) for
the boost converter and (4) for the buck converter. These results
show the slave switch turns
OFF close to where the inductor cur-
rent reaches zero and thus the D
estimation equations work well
in the real system. After the inductor current falls to zero, the
circuit experiences some voltage oscillations due to the influ-
ence of the inductor and parasitic capacitances of the switches.
These voltage oscillations cause only very small losses in each
phase, since all devices are turned
OFF and the current is al-
most zero. Furthermore, they do not overstress the devices. The
oscillations can be reduced by adding an RC snubber circuit
Fig. 5. D
estimation result in buck converter (see v
gs1
).
between each switch and transfer losses caused by oscillation
from switch to the snubber circuit. However, when observed
from input and output of the whole converter with the proposed
interleaving techniques, these oscillations will not be apparent,
even if snubber circuits are not added.
From the above equations, it is noted that the imbalance cur-
rent depends primarily on duty ratio differences and inductance
differences. However, in DCM mode, the imbalance current is
very small since each phase current starts from zero at every
switching cycle. A 1% difference in duty cycle will cause a 2%
increase of current imbalance in theory. In CCM mode, how-
ever, a 1% difference in duty cycle can cause an unacceptable
current imbalance (for example, 84% imbalance current in [12])
over time. In order to minimize the difference in each duty cy-
cle, digital controllers, such as field-programmable gate arrays
(FPGA), can generate many signals simultaneously with high
accuracy [21]. The phase shift techniques are also implemented
in the digital controller.
1144 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012
Fig. 6. Battery power requirement during urban driving for battery power
alone system.
C. Control Stage Design
There are two control stages in this energy storage system:
power distribution control stage and the converter control stage.
The power distribution control stage determines the power
distribution between ultracapacitor power and battery power.
While a vehicle is driving, especially in urban conditions, the
power requirement changes frequently. A simulation-based bat-
tery power requirement model has been built with battery power
requirement shown in Fig. 6 [23]. The simulation was based
on local driving conditions in urban an area of Lincoln, Ne-
braska, using a 2004 Toyota Prius data with assumption of
Lithium-ion battery presented in this paper. Detailed modeling
and calculation of the battery power requirement is available in
[23].
In order to improve the battery lifetime and meet the over-
heating limitation, the ultracapacitor provides/absorbs most
peak power and the battery is kept at almost constant power.
Thus, it is important to ensure the ultracapacitor stores enough
power to release during acceleration, and has enough room to
absorb power during braking. A system control strategy has
been designed to keep the ultracapacitor voltage in a range at
different vehicle speeds as in reference [24] and shown in Fig. 7.
According to the ultracapacitor voltage, the battery SOC and the
traction demand power, the control system gives out the demand
power for dc/dc converter.
The converter control stage will generate the driving signals
for the 16 phases according to dc/dc converter demand power,
that is, in total 32 gate signals need to be generated. Using
digital control, these pulses can be timed to a high accuracy level
such that the differences of duty ratio between each phase are
very small and the imbalance current can be minimized. Thus,
a current control loop in each phase can be removed and the
complexity of control circuit can be reduced. The main switch
duty ratio can be calculated by (1) in boost mode and (3) in buck
mode in the open-loop control system. Also, the control can be
achieved by a simple proportional-integral controller (PI) in
the closed-loop control system. The duty ratio of freewheeling
Fig. 7. Ultracapacitor voltage working range at different vehicle speed (be-
tween Va and Vd). Va is the voltage to ensure that ultracapacitor can provide
enough power for acceleration; Vd is voltage to ensure that ultracapacitor has
enough room to absorb power during braking.
Fig. 8. Phase-shifter structure implemented in an FPGA.
transistor is calculated by (2) in boost mode and (4) in buck
mode. Each driving signal is shifted from the previous one.
The gate signals are generated by making a comparison be-
tween the duty cycle and the counter. Each phase has its own
counter. The phase shift is achieved by controlling the value of
the counter. The phase-shifter structure is shown in Fig. 8. There
is a main counter, with the calculation of other counters based on
it (see CT
0
in Fig. 8.). For the main switch in each phase, these
subordinate counters are the value of the main counter minus
some constants to get subordinate counter values, and then each
is compared to the duty cycle. The main switch counter CT
i
and
constants C
i
to be added are:
CT
i
= CT
0
− C
i
(5)
C
i
=
i · C
p
N +1
. (6)
For the slave switch of each phase, the counter value can be
calculated as
CT
i
= CT
i
− D − DT (7)
where, i is the phase number, (N+1) is the number of the phase,
C
p
is the resolution of the period which is equal to the range of
the counter, and DT is the dead time.
