Journal ArticleDOI
Latchup-free ESD protection design with complementary substrate-triggered SCR devices
Ming-Dou Ker,Kuo-Chun Hsu +1 more
TLDR
In this article, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed.Abstract:
The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.read more
Citations
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New Design on 2×VDD-Tolerant Power-Rail ESD Clamp Circuit with Low Standby Leakage in 65nm
Chih-Ting Yeh,Ming-Dou Ker +1 more
TL;DR: A 2×VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit with only thin gate oxide 1V devices and silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process.
Characterization of ESD protection structures for 65 nm CMOS technology
TL;DR: In this paper, the authors deal with failures induced by ESD phenomena, starting from the description of main charging events up to the physics beyond the operation of different devices under high current regime.
Journal ArticleDOI
Simulation of Three Phase Soft Starter using Multiple SCRS
TL;DR: In this article, the authors presented a motor soft starter using only multiple SCRs, which decreases the dimension, density and reduces the amount of SCR. Simulation result of future topology is compared with the conventional topology.
Proceedings ArticleDOI
A Study on Output Bit Tampering of True Random Number Generators Using Time-Varying EM Waves
Saki Osuka,Daisuke Fujimoto,Arthur Beckers,Benedikt Gierlichs,Ingrid Verbauwhede,Yu-ichi Hayashi +5 more
TL;DR: In this paper, the authors have shown the possibility of tampering with a part of the random number sequence by controlling the electromagnetic waves applied to the TERO-based TRNG, where disturbance waves are applied to TRNG to change the power supply voltage of the device.
Journal Article
Comparison And Overview Of SCR Based ESD Protection Devices For CMOS ICs
Piyush Chauhan,Amit Prakash +1 more
TL;DR: An overview of SCR based E SD protection devices is made that recounts the working function, strong parameters and drawbacks of these devices, which can be speedily referred before designing an on-chip ESD protection circuit for CMOS ICs.
References
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Book
ESD in silicon integrated circuits
TL;DR: ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESC in Integrated Circuits Effects of Processing and Packaging.
Journal ArticleDOI
Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI
TL;DR: In this paper, a whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole chip ESDprotection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits.
Journal ArticleDOI
A low-voltage triggering SCR for on-chip ESD protection at output and input pads
Amitava Chatterjee,T. Polgreen +1 more
TL;DR: In this article, a novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented, which switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure.
Proceedings Article
GGSCRs: GGNMOS Triggered silicon controlled rectifiers for ESD protection in deep sub-micron CMOS processes
Cornelius Christian Russ,Markus Paul Josef Mergens,K. Verhaege,John Armer,Phillip Czeslaw Jozwiak,G. Kolluri,Leslie Ronald Avery +6 more
TL;DR: A novel Grounded-Gate NMOS Triggered SCR device (GGSCR) is introduced and compared to the LVTSCR, demonstrating that GGSCRs can fulfill all ESD protection requirements for todays IC applications in different 0.25 um, 0.18 um and 0.13 um CMOS processes.