Journal ArticleDOI
Latchup-free ESD protection design with complementary substrate-triggered SCR devices
Ming-Dou Ker,Kuo-Chun Hsu +1 more
TLDR
In this article, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed.Abstract:
The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.read more
Citations
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Journal ArticleDOI
Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
Ming-Dou Ker,Kuo-Chun Hsu +1 more
TL;DR: An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented and the solutions to overcome latchup issue in the SCR-based devices are discussed.
Journal ArticleDOI
High Holding Voltage SCR-LDMOS Stacking Structure With Ring-Resistance-Triggered Technique
TL;DR: In this article, a ring-resistance-triggered stacked SCR-laterally diffused MOS was verified in a 0.35 μm, 30-V/5-V bipolar CMOS DMOS process to solve the coupling of trigger voltage and holding voltage.
Patent
Initial-on scr device for on-chip esd protection
TL;DR: In this paper, a semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR), a substrate, a gate, a first diffused region, and a second diffused regions separated apart from the first region.
Journal ArticleDOI
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology
Chang-Tzu Wang,Ming-Dou Ker +1 more
TL;DR: In this paper, an ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, was proposed with consideration of gate current to reduce the standby leakage current.
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale
Chang-Tzu Wang,Ming-Dou Ker +1 more
TL;DR: An ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, has been proposed with consideration of gate current to reduce the standby leakage current.
References
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Proceedings ArticleDOI
Internal chip ESD phenomena beyond the protection circuit
TL;DR: In this article, I/O protection is not effective due to interaction with the internal chip layout, and induced current paths can exist when outputs/inputs are stressed with respect to V/sub DD/ or V/ sub SS/ stress.
Journal ArticleDOI
ESD protection to overcome internal gate oxide damage on digital-analog interface of mixed-mode CMOS IC's
Ming-Dou Ker,Ta-Lee Yu +1 more
TL;DR: In this article, a new ESD protection method is proposed to rescue this internal gate-oxide damage by adding ESD-protection devices on the long metal line between digital-analog interfaces.
Proceedings ArticleDOI
Antenna protection strategy for ultra-thin gate MOSFETs
Srikanth Krishnan,A. Amerasekera +1 more
TL;DR: In this article, the efficacy of drain-well and gated diodes as antenna protection under positive as well as negative plasma damage for gate oxides down to 21 /spl Aring was compared.
Journal ArticleDOI
ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins
TL;DR: In this paper, the authors reported a real case of electrostatic discharge (ESD) improvement on a complementary metal oxide semiconductor integrated circuit (IC) product with multiple separated power pins.
Journal ArticleDOI
Unique ESD failure mechanisms during negative to Vcc HBM tests
TL;DR: In this paper, HBM ESD tests on two types of 0.6 μm DRAM devices showed that internal circuit or output driver failures would occur after the input or I/O pins were ESD stressed negative with respect to Vcc at ground.