Journal ArticleDOI
Latchup-free ESD protection design with complementary substrate-triggered SCR devices
Ming-Dou Ker,Kuo-Chun Hsu +1 more
TLDR
In this article, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed.Abstract:
The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.read more
Citations
More filters
Journal ArticleDOI
A novel DTSCR with a variation lateral base doping structure to improve turn-on speed for ESD protection
TL;DR: In this article, a double trigger silicon controlled rectifier device (DTSCR) with a variation lateral base doping (VLBD) structure was proposed for ESD protection applications.
Patent
An electrostatic discharge protection device comprising a silicon controlled rectifier
TL;DR: In this article, the authors proposed an electrostatic discharge protection device including a silicon controlled rectifier, which includes a first n-type region and a p-type contact region.
Proceedings ArticleDOI
Comparison of different MOS-triggered SCR structures for on-chip ESD protection
TL;DR: In this article, three types of MOS-triggered SCR structures, namely, Merged MOS, compact MOS and boundary-MOS, have been fabricated and compared in 0.13 µm CMOS process for on-chip ESD protection.
Proceedings ArticleDOI
Initial-On ESD Protection Design with PMOS-Triggered SCR Device
Ming-Dou Ker,Shih-Hung Chen +1 more
TL;DR: In this article, an initial-on SCR design with PMOS-triggered SCR was proposed to achieve the lowest trigger voltage and the fastest turn-on speed of SCR device for effective on-chip ESD protection.
Journal ArticleDOI
A Novel Voltage Divider Trigger SCR With Low Leakage Current for Low-Voltage ESD Application
TL;DR: In this article , a voltage divider trigger silicon-controlled rectifier (VDTSCR) with low trigger voltage and low leakage current for electrostatic discharge protection applications has been proposed and verified in a 65-nm epitaxial CMOS process.
References
More filters
Book
ESD in silicon integrated circuits
TL;DR: ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESC in Integrated Circuits Effects of Processing and Packaging.
Journal ArticleDOI
Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI
TL;DR: In this paper, a whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole chip ESDprotection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits.
Journal ArticleDOI
A low-voltage triggering SCR for on-chip ESD protection at output and input pads
Amitava Chatterjee,T. Polgreen +1 more
TL;DR: In this article, a novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented, which switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure.
Proceedings Article
GGSCRs: GGNMOS Triggered silicon controlled rectifiers for ESD protection in deep sub-micron CMOS processes
Cornelius Christian Russ,Markus Paul Josef Mergens,K. Verhaege,John Armer,Phillip Czeslaw Jozwiak,G. Kolluri,Leslie Ronald Avery +6 more
TL;DR: A novel Grounded-Gate NMOS Triggered SCR device (GGSCR) is introduced and compared to the LVTSCR, demonstrating that GGSCRs can fulfill all ESD protection requirements for todays IC applications in different 0.25 um, 0.18 um and 0.13 um CMOS processes.