Journal ArticleDOI
Latchup-free ESD protection design with complementary substrate-triggered SCR devices
Ming-Dou Ker,Kuo-Chun Hsu +1 more
TLDR
In this article, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed.Abstract:
The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.read more
Citations
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Journal ArticleDOI
Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
Ming-Dou Ker,Kuo-Chun Hsu +1 more
TL;DR: An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented and the solutions to overcome latchup issue in the SCR-based devices are discussed.
Journal ArticleDOI
High Holding Voltage SCR-LDMOS Stacking Structure With Ring-Resistance-Triggered Technique
TL;DR: In this article, a ring-resistance-triggered stacked SCR-laterally diffused MOS was verified in a 0.35 μm, 30-V/5-V bipolar CMOS DMOS process to solve the coupling of trigger voltage and holding voltage.
Patent
Initial-on scr device for on-chip esd protection
TL;DR: In this paper, a semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR), a substrate, a gate, a first diffused region, and a second diffused regions separated apart from the first region.
Journal ArticleDOI
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology
Chang-Tzu Wang,Ming-Dou Ker +1 more
TL;DR: In this paper, an ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, was proposed with consideration of gate current to reduce the standby leakage current.
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale
Chang-Tzu Wang,Ming-Dou Ker +1 more
TL;DR: An ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, has been proposed with consideration of gate current to reduce the standby leakage current.
References
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Proceedings ArticleDOI
Electrostatic discharge protection circuits in CMOS ICs using the lateral SCR devices: an overview
TL;DR: An overview on the electrostatic discharge (ESD) protection circuits by using the lateral SCR devices in CMOS ICs is presented and two solutions are proposed to safely apply theSCR devices for effective ESD protection in the CMOSICs.
Proceedings ArticleDOI
ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins
TL;DR: In this article, the authors reported a real case for ESD level improvement on a CMOS IC product with multiple separated power pins, which can be improved from the original 0.5 kV to 3 kV by adding an extra ESD clamp with a channel width of 10 /spl mu/m between the interface node and ground line.
Proceedings ArticleDOI
On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process
Ming-Dou Ker,Kuo-Chun Hsu +1 more
TL;DR: The on-chip ESD protection circuits designed with the substrate-triggered SCR devices for input pad, output pad, and power pad have been successfully verified in a 0.25 /spl mu/m CMOS process.
Proceedings ArticleDOI
Complementary substrate-triggered SCR devices for on-chip ESD protection circuits
Ming-Dou Ker,Kuo-Chun Hsu +1 more
TL;DR: In this article, the complementary substrate-triggered SCR devices, which are a combination of the substrate-triggering technique and SCR device, are first reported in the literature for use in on-chip ESD protection circuits.