Journal ArticleDOI
Limitations and challenges of multigigabit DRAM chip design
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TLDR
In this article, the limitations and challenges involved in designing gigabit DRAM chips in terms of high-density devices, high-performance circuits, and low power/lowvoltage circuits are described.Abstract:
This paper describes the limitations and challenges involved in designing gigabit DRAM chips in terms of high-density devices, high-performance circuits, and low-power/low-voltage circuits. The key results obtained are as follows. 1) For formation of a MOSFET shallow junction, which suppresses threshold voltage (V/sub T/) variation and offset voltage of sense amplifiers, reduction in ion-implantation energy and process temperature is essential. Also, the keys in terms of area, speed, stable cell operation, and ease of fabrication are use of low-resistivity multilevel metal wiring and high permittivity materials and three-dimensional memory cells to reduce a difference in height between the memory cell array and the surrounding peripheral circuits. 2) For creation of a high speed, the keys are memory-subsystem technology such as pipeline operation, wide-bit I/O, low-voltage interfaces, and high-density packaging. Embedded DRAM further enhances the speed and throughput by using massively parallel processing of signals on a large number of data-lines and reducing internal bus capacitances. 3) For power reduction, the key continues to be reduction of the data-line dissipating charge through both partial activation of multidivided data-lines and lowering of the data-line voltage. Ultralow-voltage operation, essential to drastic power reduction, can be achieved by subthreshold-current reduction circuits such as source-gate backbiasing, multi-V/sub T/, dynamic V/sub T/, and node-boosting schemes.read more
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References
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Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Journal ArticleDOI
Trends in low-power RAM circuit technologies
K. Itoh,K. Sasaki,Y. Nakagome +2 more
TL;DR: In this article, a general description of power sources in a RAM chip, and covers both DRAMs and SRAMs, is discussed, and the authors also show that the application of subthreshold current reduction circuits (such as source-gate back biasing) to cell and iterative circuit blocks is indispensable in the future.
Proceedings ArticleDOI
A capacitor-over-bit-line (COB) cell with a hemispherical-grain storage node for 64 Mb DRAMs
Masato Sakao,Naoki Kasai,T. Ishijima,Eiji Ikawa,Hirohito Watanabe,K. Terada,Takamaro Kikkawa +6 more
TL;DR: In this paper, a capacitor-over-bit-line (COB) cell with a hemispherical-grain (HSG) poly-Si storage node has been developed.
Journal ArticleDOI
A 40 nm gate length n-MOSFET
TL;DR: In this article, a 40 mm gate length n-MOSFET with ultra-shallow source and drain junctions of around 10 nm was fabricated for the first time.
Journal ArticleDOI
Crown-shaped stacked-capacitor cell for 1.5-V operation 64-Mb DRAMs
Toru Kaga,Tokuo Kure,H. Shinriki,Yoshifumi Kawamoto,Fumio Murai,Takashi Nishida,Y. Nakagome,Digh Hisamoto,T. Kisu,Eiji Takeda,K. Itoh +10 more
TL;DR: In this paper, a self-aligned stacked-capacitor cell called the CROWN cell was developed for experimental 64-Mb-DRAMs operated at 1.5 V.