Open AccessProceedings Article
Low-power and robust six-FinFET memory cell using selective gate-drain/source overlap engineering
S.A. Tawfik,Volkan Kursun +1 more
- pp 244-247
TLDR
In this article, a new FinFET memory circuit technique based on gate-drain/source overlap engineering is proposed to enhance the read stability of the proposed SRAM circuit.Abstract:
A new FinFET memory circuit technique based on gate-drain/source overlap engineering is proposed in this paper The read stability of the proposed SRAM circuit is enhanced by 53% and the leakage power is reduced by 48% as compared to a minimum sized low-threshold-voltage FinFET SRAM cell in a 32nm FinFET technology Furthermore, the layout area of the proposed SRAM circuit is reduced by 17% as compared to a FinFET SRAM circuit with longer-channel access transistors The proposed technique based on gate-drain/source overlap engineering is easier to be implemented with fewer processing steps as compared to the previously published data stability enhancement techniques based on independent-gate bias and gate work-function engineering in FinFET memory circuitsread more
Citations
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Journal ArticleDOI
Dual- $V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits
M Rostami,Kartik Mohanram +1 more
TL;DR: This paper describes the electrode work-function, oxide thickness, gate-source/drain underlap, and silicon thick ness optimization required to realize dual-Vth independent-gate FinFETs, enabling a new class of compact logic gates with higher expressive power and flexibility than conventional CMOS gates.
Proceedings ArticleDOI
Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs
TL;DR: This paper investigates the fault behaviors of the gate oxide short in FinFETs using TCAD mixed-mode simulations and proposes two new test methods that prove the two methods' test efficacy of detecting the Gate oxide shorts uncovered by traditional test methods.
Journal ArticleDOI
FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability
TL;DR: In this article, two new asymmetric bitline access transistors are proposed for achieving enhanced read data stability and lower leakage power consumption in memory circuits, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells.
Proceedings ArticleDOI
Low-leakage hybrid FinFET SRAM cell with asymmetrical gate overlap / underlap bitline access transistors for enhanced read data stability
TL;DR: The read data stability is enhanced and the leakage power consumption is reduced by up to 62% while maintaining similar write margin, cell layout area, read delay, and write delay as compared to a previously published asymmetrical six-FinFET SRAM cell in a 15nm FinFET technology.
Proceedings ArticleDOI
Asymmetrical FinFET SRAM cells with wider read noise margin and lower leakage currents
TL;DR: In this paper, two new FinFET memory circuits with asymmetrically gate underlap transistors are proposed for achieving stronger read data stability and lower leakage power consumption. But the performance of the proposed asymmetric six-transistor SRAM cells is limited.
References
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Journal ArticleDOI
Static-noise margin analysis of MOS SRAM cells
TL;DR: In this article, the stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation, and explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived.
Journal ArticleDOI
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply
Kevin Zhang,Uddalak Bhattacharya,Zhanping Chen,Fatih Hamzaoglu,D. Murray,N. Vallepalli,Yih Wang,B. Zheng,M. Bohr +8 more
TL;DR: In this article, a column-based dynamic power supply has been integrated into a high-frequency 70-Mb SRAM design that is fabricated on a high performance 65-nm CMOS technology.
Proceedings ArticleDOI
Leakage-Aware Design of Nanometer SoC
TL;DR: New low-leakage circuit techniques based on multi-threshold-voltage and multi-oxide-thickness standard single-gate and emerging double-gate MOSFET/FinFET technologies are presented in this paper.
Journal ArticleDOI
Design Optimization and Performance Projections of Double-Gate FinFETs With Gate–Source/Drain Underlap for SRAM Application
Seung-Hwan Kim,Jerry G. Fossum +1 more
TL;DR: In this article, the authors used physical device/circuit simulations to explore 6T-SRAM cell design and scaling using double-gate (DG) FinFETs with optimized gate-source/drain underlap.
Proceedings ArticleDOI
Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits
S.A. Tawfik,Volkan Kursun +1 more
TL;DR: The use of work-function engineering to control the threshold voltage of FinFETs is explored in this paper for achieving minimum sized multi-threshold-voltage (multi-Vt) six transistor (6T) SRAM cells with sufficient data stability and lower leakage power consumption characteristics.