Proceedings ArticleDOI
Low Power Scan Shift and Capture in the EDT Environment
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TLDR
A flexible test application framework that achieves significant reductions in switching activity during all phases of scan test: scan loading, unloading, and capture is presented.Abstract:
This paper presents a new and comprehensive power-aware test scheme compatible with a test compression environment. The key contribution of the paper is a flexible test application framework that achieves significant reductions in switching activity during all phases of scan test: scan loading, unloading, and capture.read more
Citations
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Journal ArticleDOI
Low-Power Scan Operation in Test Compression Environment
TL;DR: A new on-chip continuous-flow decompressor that integrates seamlessly with test logic synthesis flow, and it fits well into various design paradigms, including modular design flow where blocks come with individual decompressors and compactors.
Proceedings ArticleDOI
On simultaneous shift- and capture-power reduction in linear decompressor-based test compression environment
TL;DR: This work proposes a generic framework for test power reduction in linear decompressor-based test compression environment, which is able to effectively reduce shift-and capture-power simultaneously and significantly outperform existing solutions.
Journal ArticleDOI
QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test
Chao-Wen Tzeng,Shi-Yu Huang +1 more
TL;DR: This paper presents an X-fill scheme that properly utilizes the don't-care bits in test patterns to simultaneously reduce the test time as well as the test power (including both capture power and shifting power).
Journal ArticleDOI
Trimodal Scan-Based Test Paradigm
TL;DR: The experimental results obtained for large and complex industrial application-specific IC designs illustrate the feasibility of the proposed test scheme despite additional costs and efforts entailed in consolidating architectural changes and operations across a DFT flow.
Proceedings ArticleDOI
Capture power reduction using clock gating aware test generation
TL;DR: By taking advantage of the existing clock gating circuitry and selectively holding the value of some scan flip-flops, switching activity during the capture cycles of a test can be reduced.
References
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Proceedings ArticleDOI
A distributed BIST control scheme for complex VLSI devices
TL;DR: A BIST scheduling process that takes into consideration constraints is presented, and a new BIST control methodology is introduced, that implements the BIST schedule with a highly modular architecture.
Journal ArticleDOI
Embedded deterministic test
TL;DR: This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.
Journal ArticleDOI
Survey of Test Vector Compression Techniques
TL;DR: This article summarizes and categories hardware-based test vector compression techniques for scan architectures, which fall broadly into three categories: code-based schemes use data compression codes to encode test cubes; linear-decompression- based schemes decompress the data using only linear operations; and broadcast-scan-based scheme rely on broadcasting the same values to multiple scan chains.
Proceedings ArticleDOI
Static compaction techniques to control scan vector power dissipation
TL;DR: It is shown here that by carefully selecting the order in which pairs of test cubes are merged during static compaction, both average power and peak power for the final test set can be greatly reduced.
Journal ArticleDOI
Techniques for minimizing power dissipation in scan and combinational circuits during test application
TL;DR: Heuristics with good performance bounds can be derived for combinational circuits tested using built-in self-test (BIST) and considerable reduction in power dissipation can be obtained using the proposed techniques.