Journal ArticleDOI
Miller and noise effects in a synchronizing flip-flop
C. Dike,Edward A. Burton +1 more
TLDR
In this paper, the effects of Miller coupling and thermal noise on a synchronizing flip-flop are described and a worst case mean-time-between-failure bound is established.Abstract:
The effects of Miller coupling and thermal noise on a synchronizing flip-flop are described. Data on the metastability characteristics of the flip-flop are gathered and analyzed. True metastability is distinguished from the deterministic region. A worst case mean-time-between-failure bound is established. A simple and accurate test method is presented. A simple jamb latch was used with driving circuits of two different strengths to determine the role of input strength on T/sub m/ and /spl tau/. The flip-flop was fabricated on a 0.25-/spl mu/m CMOS process.read more
Citations
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Proceedings ArticleDOI
Metastability testing at FPGA circuit design using propagation time characterization
TL;DR: The measurement method and experimental technique with advanced instrumentation setup for analysing the metastability behavior and performance measurement of flip-flops used in programmable logic devices and the same test methods can be used for evaluation of timing reliability in digital circuits as well.
Proceedings ArticleDOI
A new 65nm LP metastability measurment test circuit
Salomon Beer,Ran Ginosar +1 more
TL;DR: In this article, the behavior of synchronizers in a broad range of supply voltage and temperature corners is studied and compared to simulations for a fabricated 65nm bulk CMOS circuit build.
Proceedings ArticleDOI
Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs
TL;DR: This paper implements a physical true random number generator (TRNG) using an SR latch on 40 nm CMOS ASIC that has a robustness against environmental change and is suitable for embedded systems to improve security in IoT systems.
Book ChapterDOI
Fast Universal Synchronizers
TL;DR: This work clarifies how such a simple "two-flop" synchronizer can be used in the system, and analyzes its performance, showing that the data cycle may be as long as 12 clock cycles.
Contributions to Asynchronous Communication Ports for GALS Systems
TL;DR: Digital systems commonly use a single global clock signal to synchronize the whole system, but this is not always possible and it can be more advantageously to divide the system into separate clock domes.
References
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Journal ArticleDOI
Metastability of CMOS latch/flip-flop
Lee-Sup Kim,Robert W. Dutton +1 more
TL;DR: In this article, the authors used the AC small-signal analysis in the frequency domain instead of the usual time-domain approach to obtain the optimal device size, aspect ratio, and configurations for the design of the metastable hardened CMOS latch/flip-flops.
Journal ArticleDOI
Synchronization reliability in CMOS technology
TL;DR: In this article, the synchronization performance of CMOS circuits is examined theoretically and experimentally, and the phase characteristics of metastability are identified, and experimental measurements of error rate are made on a CMOS test circuit and the gain-bandwidth product for the circuit is determined.
Journal ArticleDOI
A fast resolving BiNMOS synchronizer for parallel processor interconnect
TL;DR: In this paper, the authors describe the design, testing, and application of a BiNMOS metastability resolving synchronizer, which reduces metastability failure with a high gain-bandwidth product and longer settling time per clock cycle.