Journal ArticleDOI
Miller and noise effects in a synchronizing flip-flop
C. Dike,Edward A. Burton +1 more
TLDR
In this paper, the effects of Miller coupling and thermal noise on a synchronizing flip-flop are described and a worst case mean-time-between-failure bound is established.Abstract:
The effects of Miller coupling and thermal noise on a synchronizing flip-flop are described. Data on the metastability characteristics of the flip-flop are gathered and analyzed. True metastability is distinguished from the deterministic region. A worst case mean-time-between-failure bound is established. A simple and accurate test method is presented. A simple jamb latch was used with driving circuits of two different strengths to determine the role of input strength on T/sub m/ and /spl tau/. The flip-flop was fabricated on a 0.25-/spl mu/m CMOS process.read more
Citations
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Book ChapterDOI
Fault-tolerant algorithms for tick-generation in asynchronous logic: robust pulse generation
TL;DR: In this article, a Byzantine fault-tolerant self-stabilizing pulse synchronization protocol is proposed for hardware designs like systemson-chip for critical applications, which facilitates a direct implementation in standard asynchronous digital logic.
Proceedings ArticleDOI
Design of a GALS Wrapper for Network on Chip
TL;DR: The simulation results show that the wrapper provides fast and reliable asynchronous communication services for the subsystems working with different clocks in NoC.
Journal ArticleDOI
A Model for Supply Voltage and Temperature Variation Effects on Synchronizer Performance
Salomon Beer,Ran Ginosar +1 more
TL;DR: A new model for the metastability time constant (τ), the metastable window (TW), and MTBF is presented and design guidelines that account for supply voltage and temperature variations and determine the correct number of synchronizer stages required for target MTBF are proposed.
Proceedings ArticleDOI
HEX: scaling honeycombs is easier than scaling clock trees
TL;DR: It is argued that grid structures are a very promising alternative to the standard approach for distributing a clock signal throughout VLSI circuits and other hardware devices, and based on a hexagonal grid with simple intermediate nodes, which both control the forwarding of clock ticks in the grid and supply them to nearby functional units.
Proceedings ArticleDOI
Reconfigurable time interval measurement circuit incorporating a programmable gain time difference amplifier
TL;DR: A reconfigurable TIM is designed with an adjustable resolution range of 15 down to 0.5 ps and a measurement dynamic range of 480 to 16 ps to perform a variety of time related measurements which require different test specifications.
References
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Journal ArticleDOI
Metastability of CMOS latch/flip-flop
Lee-Sup Kim,Robert W. Dutton +1 more
TL;DR: In this article, the authors used the AC small-signal analysis in the frequency domain instead of the usual time-domain approach to obtain the optimal device size, aspect ratio, and configurations for the design of the metastable hardened CMOS latch/flip-flops.
Journal ArticleDOI
Synchronization reliability in CMOS technology
TL;DR: In this article, the synchronization performance of CMOS circuits is examined theoretically and experimentally, and the phase characteristics of metastability are identified, and experimental measurements of error rate are made on a CMOS test circuit and the gain-bandwidth product for the circuit is determined.
Journal ArticleDOI
A fast resolving BiNMOS synchronizer for parallel processor interconnect
TL;DR: In this paper, the authors describe the design, testing, and application of a BiNMOS metastability resolving synchronizer, which reduces metastability failure with a high gain-bandwidth product and longer settling time per clock cycle.