Journal ArticleDOI
Miller and noise effects in a synchronizing flip-flop
C. Dike,Edward A. Burton +1 more
TLDR
In this paper, the effects of Miller coupling and thermal noise on a synchronizing flip-flop are described and a worst case mean-time-between-failure bound is established.Abstract:
The effects of Miller coupling and thermal noise on a synchronizing flip-flop are described. Data on the metastability characteristics of the flip-flop are gathered and analyzed. True metastability is distinguished from the deterministic region. A worst case mean-time-between-failure bound is established. A simple and accurate test method is presented. A simple jamb latch was used with driving circuits of two different strengths to determine the role of input strength on T/sub m/ and /spl tau/. The flip-flop was fabricated on a 0.25-/spl mu/m CMOS process.read more
Citations
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Proceedings ArticleDOI
Register-communication between mutually asynchronous domains
TL;DR: This work presents the design of several so-called communication registers, which are modules that support non-blocking communication between two mutually asynchronous domains, and distinguishes four different kinds of modules: one for each possible access port combination.
Proceedings ArticleDOI
Synchronizer Performance in Deep Sub-Micron Technology
TL;DR: It is shown that the performance characteristics of synchronizer circuits track fabrication feature size reductions in a similar manner to the fan-out-of-four, FO4, inverter delay.
A dual-clock fifo for the reliable transfer of high-throughput data between unrelated clock domains
TL;DR: This thesis presents an encompassing description of the motivation and design decisions for a robust and scalable dual-clock FIFO architecture that utilizes an efficient and low-latency memory array structure and can operate in applications where multiple clock cycles of latency exist between the data producer, FifO, and the data consumer.
Proceedings ArticleDOI
Analysing the effect of process variation to reduce parametric yield loss
TL;DR: In this paper, a combination of two statistical tools, namely Design of Experiments (DoE) and Response Surface Modeling (RSM), is used to identify and model those process parameters whose variation which will impact most on the performance of a circuit.
Opportunities for Fine-Grained Adaptive Voltage Scaling to Improve System-Level Energy Efficiency
Ben Keller,Borivoje Nikolic +1 more
TL;DR: Applying the energy model to traces of a cycle-accurate processor system simulation predicts energy savings of up to 53% from the application of fine-grained DVFS techniques.
References
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Journal ArticleDOI
Metastability of CMOS latch/flip-flop
Lee-Sup Kim,Robert W. Dutton +1 more
TL;DR: In this article, the authors used the AC small-signal analysis in the frequency domain instead of the usual time-domain approach to obtain the optimal device size, aspect ratio, and configurations for the design of the metastable hardened CMOS latch/flip-flops.
Journal ArticleDOI
Synchronization reliability in CMOS technology
TL;DR: In this article, the synchronization performance of CMOS circuits is examined theoretically and experimentally, and the phase characteristics of metastability are identified, and experimental measurements of error rate are made on a CMOS test circuit and the gain-bandwidth product for the circuit is determined.
Journal ArticleDOI
A fast resolving BiNMOS synchronizer for parallel processor interconnect
TL;DR: In this paper, the authors describe the design, testing, and application of a BiNMOS metastability resolving synchronizer, which reduces metastability failure with a high gain-bandwidth product and longer settling time per clock cycle.