Journal ArticleDOI
Miller and noise effects in a synchronizing flip-flop
C. Dike,Edward A. Burton +1 more
TLDR
In this paper, the effects of Miller coupling and thermal noise on a synchronizing flip-flop are described and a worst case mean-time-between-failure bound is established.Abstract:
The effects of Miller coupling and thermal noise on a synchronizing flip-flop are described. Data on the metastability characteristics of the flip-flop are gathered and analyzed. True metastability is distinguished from the deterministic region. A worst case mean-time-between-failure bound is established. A simple and accurate test method is presented. A simple jamb latch was used with driving circuits of two different strengths to determine the role of input strength on T/sub m/ and /spl tau/. The flip-flop was fabricated on a 0.25-/spl mu/m CMOS process.read more
Citations
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Journal Article
Asynchronizer Based Wireless Sensor System
V. Umasankar,K. Suganthi +1 more
TL;DR: The detailed aim of GALS wrapper is given and the circuits are verified with Verlog-HDL and executed in FPGA and shows that the wrapper provides fast and consistent communication for the subsystems working with different clocks of NoC.
Dissertation
Réflexions autour de la méthodologie de vérification des circuits multi-horloges : analyse qualitative et automatisation
TL;DR: In this article, the Clock Domain Crossing (CDC) has been investigated in the context of verification in an industrial setting, where the authors propose a verification approach based on the specification of contraintes and exclusions by l'utilisateur.
Proceedings ArticleDOI
Notice of Violation of IEEE Publication Principles Delayed Latching for Data Synchronization in GALS SOC
V. E. Khetade,S. S. Limaye +1 more
TL;DR: An in-depth analysis of the problem and a novel solution is proposed for synchronizing inter-modular communications in GALS, based on delayed latching, which replaces complex global timing constraints with simpler localized ones.
References
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Journal ArticleDOI
Metastability of CMOS latch/flip-flop
Lee-Sup Kim,Robert W. Dutton +1 more
TL;DR: In this article, the authors used the AC small-signal analysis in the frequency domain instead of the usual time-domain approach to obtain the optimal device size, aspect ratio, and configurations for the design of the metastable hardened CMOS latch/flip-flops.
Journal ArticleDOI
Synchronization reliability in CMOS technology
TL;DR: In this article, the synchronization performance of CMOS circuits is examined theoretically and experimentally, and the phase characteristics of metastability are identified, and experimental measurements of error rate are made on a CMOS test circuit and the gain-bandwidth product for the circuit is determined.
Journal ArticleDOI
A fast resolving BiNMOS synchronizer for parallel processor interconnect
TL;DR: In this paper, the authors describe the design, testing, and application of a BiNMOS metastability resolving synchronizer, which reduces metastability failure with a high gain-bandwidth product and longer settling time per clock cycle.