Modeling and simulation of hot-carrier-induced device degradation in MOS circuits

TLDR: In this article, an integrated simulation tool is presented for estimating the hot-carrier-induced degradation of nMOS transistor characteristics and circuit performance and a reliability simulation tool incorporates an accurate one-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors.

Abstract: The physical models and an integrated simulation tool are presented for estimating the hot-carrier-induced degradation of nMOS transistor characteristics and circuit performance. The proposed reliability simulation tool incorporates an accurate one-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors. The hot-carrier-induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. The physical degradation model includes both fundamental device degradation mechanisms, i.e., charge trapping and interface trap generation. A repetitive simulation scheme has been adopted to ensure accurate prediction of the circuit-level degradation process under dynamic operating conditions. >