Proceedings ArticleDOI
Optimization of VDD and VTH for low-power and high speed applications
K. Nose,Takayasu Sakurai +1 more
- pp 469-474
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TLDR
In this paper, closed-form formulas are presented for optimum supply voltage (VDD) and threshold voltage (VTH) that minimize power dissipation when technology parameters and required speed are given.Abstract:
Closed-form formulas are presented for optimum supply voltage (VDD) and threshold voltage (VTH) that minimize power dissipation when technology parameters and required speed are given. The formulas take into account short-channel effects and the variation of VTH and temperature. Using typical device parameters, it is shown that a simple guideline to optimize the power consumption is to set the ratio of maximum leakage power to total power about 30%. Extending the analysis, the future VLSI design trend is discussed. The optimum VDD coincides with the SIA roadmap and the optimum VTH for logic blocks at the highest temperature and at the lowest process variation corner is in the range of 0V~0.1V over generations.read more
Citations
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Scaling, power, and the future of CMOS
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References
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Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Journal ArticleDOI
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
Takayasu Sakurai,A.R. Newton +1 more
TL;DR: In this paper, an alpha-power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced and closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived.
Journal ArticleDOI
Supply and threshold voltage scaling for low power CMOS
TL;DR: In this paper, the authors investigated the effect of reducing the supply and threshold voltage on the energy efficiency of CMOS circuits and showed that when the transistors are velocity saturated and the nodes have a high activity factor, this simple analysis suggests optimal energy efficiency at supply voltages under 0.5 V.
Journal Article
Ultra low power CMOS technology
J. Burr,A. Peterson +1 more
TL;DR: The motivation, opportunities, and problems associated with implementing digital logic at very low voltages, including the challenge of making use of the available real estate in 3D multichip modules, and energy requirements of very large neural networks are discussed.
Journal ArticleDOI
Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs
TL;DR: In this article, the authors describe possible temperature instability in the low-voltage regime by using circuit simulation environments incorporating temperature change in time and experiments using MOSFET's and 32-bit adder circuit in quarter micron CMOS technology with low threshold voltage of 0.25 V.
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