Journal ArticleDOI
Simulation and optimization of EJ-MOSFETs
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TLDR
In this article, a simulation of EJ-MOSFETs with a channel length of 50 nm, source-drain distance between 150 nm and 9 μm, and different channel dopings have been systematically investigated by means of 2D device simulation.Abstract:
Electrically variable shallow junction (EJ) MOSFETs with a channel length of 50 nm, source–drain distances between 150 nm and 9 μm, and different channel dopings have been systematically investigated by means of 2D device simulation. SOI EJ-MOSFETs with a highly doped channel show a subthreshold behavior similar to the comparable bulk version. By decreasing the source–drain distance down to 150 nm and lowering the channel doping the on-currents of EJ-MOSFETs can be increased by more than two orders of magnitude.read more
Citations
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Journal ArticleDOI
Modeling and simulation of a nanoscale three-region tri-material gate stack (TRIMGAS) MOSFET for improved carrier transport efficiency and reduced hot-electron effects
TL;DR: In this paper, a two-dimensional analytical modeling for a novel multiple region MOSFET device architecture is presented, which shows reduced short-channel effects at short gate lengths, using a three-region analysis in the horizontal direction and a universal depletion width boundary condition.
Journal ArticleDOI
Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension
Cong Li,Yiqi Zhuang,Ru Han +2 more
TL;DR: It is demonstrated that the proposed structure exhibits better suppression of short channel effects and hot carrier effects when compared to the conventional cylindrical surrounding gate MOSFETs.
Journal ArticleDOI
Analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions
TL;DR: Results show that the application of electrically induced S/D extensions to the cylindrical surrounding-gate MOSFET will successfully suppress the hot-carrier effects, threshold voltage roll-off, and DIBL.
Journal ArticleDOI
Performance optimization of electrically variable double gate junctionless transistor with HfO2 gate dielectric
Achinta Baidya,Lalchhuanawma Ralte,Lalramnunmawia Khawlhring,Zosangzeli,Pritam Nikam,Niladri Pratap Maity +5 more
TL;DR: In this article , an electrically variable double-gate nano-scale junctionless transistor was proposed and a simulation study of the proposed structure is performed to understand its performance, which shows that improvement in transconductance can be achieved in sub-threshold region with the variation in side gate voltages.
Proceedings ArticleDOI
Modeling of vertical transistor with electrically variable junctions in ISE TCAD
TL;DR: In this article, the authors present the results of simulation of a vertical MOS transistor with electrically variable shallow junctions in ISE TCAD and show that the use of such junctions really suppresses short channel effects and reduces direct leakage current.
References
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Proceedings ArticleDOI
Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime
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Proceedings ArticleDOI
Design and performance considerations for sub-0.1 /spl mu/m double-gate SOI MOSFET'S
TL;DR: In this article, a simulation-based analysis of the device design and circuit performance trade-offs between short channel immunity and parasitic device capacitances of sub-1 /spl mu/m double-gate SOI MOSFET's is presented.
Journal ArticleDOI
Transistor characteristics of 14-nm-gate-length EJ-MOSFETs
TL;DR: In this paper, an electrically variable shallow junction metal-oxide-silicon field effect transistors (EJ-MOSFETs) were fabricated to investigate transport characteristics of ultrafine gate MOSFets.
Journal ArticleDOI
Vertical Si-Metal-Oxide-Semiconductor Field Effect Transistors with Channel Lengths of 50 nm by Molecular Beam Epitaxy.
TL;DR: In this paper, the growth conditions in molecular beam epitaxy (MBE) were studied for the fabrication of vertical Si-metal-oxide-semiconductor field effect transistors (MOSFET) with channel lengths down to 50 nm.