Proceedings ArticleDOI
Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime
J. Kedzierski,Peiqi Xuan,E. Anderson,Jeffrey Bokor,Tsu-Jae King,Chenming Hu +5 more
- pp 57-59
TLDR
In this article, thin-body transistors with silicide source/drains were fabricated with gate-lengths down to 15 nm and complementary low-barrier silicides were used to reduce contact and series resistance.Abstract:
Thin-body transistors with silicide source/drains were fabricated with gate-lengths down to 15 nm. Complementary low-barrier silicides were used to reduce contact and series resistance. Minimum gate-length transistors with T/sub ox/=40 /spl Aring/ show PMOS |I/sub dsat/|=270 /spl mu/A//spl mu/m and NMOS |I/sub dsat/|=190 /spl mu/A//spl mu/m with V/sub ds/=1.5 V, |V/sub g/-V/sub t/|=1.2 V and, I/sub on//I/sub off/>10/sup 4/. A simple transmission model, fitted to experimental data, is used to investigate effects of oxide scaling and extension doping.read more
Citations
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Journal ArticleDOI
Theory of ballistic nanotransistors
TL;DR: In this paper, numerical simulations are used to guide the development of a simple analytical theory for ballistic field-effect transistors, and the model reduces to Natori's theory of the ballistic MOSFET.
Journal ArticleDOI
Overview and status of metal S/D Schottky-barrier MOSFET technology
John M. Larson,John P. Snyder +1 more
TL;DR: The metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology as mentioned in this paper offers several benefits that enable scaling to sub-30-nm gate lengths.
Journal ArticleDOI
Polymer self assembly in semiconductor microelectronics
Charles T. Black,Ricardo Ruiz,Gregory Breyta,Joy Cheng,Matthew E. Colburn,Kathryn W. Guarini,Hyungjun Kim,Y. Zhang +7 more
TL;DR: Target applications including surface-roughening for on-chip decoupling capacitors, patterning nanocrystal floating gates for FLASH devices, and defining FET channel arrays are discussed.
Journal ArticleDOI
Carbon nanotube electronics
Joerg Appenzeller,Joachim Knoch,Richard Martel,Vincent Derycke,Shalom J. Wind,Phaedon Avouris +5 more
TL;DR: In this paper, single-wall carbon nanotube field effect transistors (CNFETs) operating at gate and drain voltages below 1V were investigated and it was shown that CNFET operation is controlled by Schottky barriers (SBs) in the source and drain region instead of by the nanotubes itself.
Journal ArticleDOI
The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance
TL;DR: In this article, the authors focused on scaling CMOS to its fundamental limits, determined by manufacturing, physics, and costs using new materials and nonclassical structures using new non-classical CMOS structures.
References
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Journal ArticleDOI
Work function of boron-doped polycrystalline Si/sub x/Ge/sub 1-x/ films
TL;DR: In this article, the work function of p-type polycrystalline Si/sub x/Ge/sub 1-x/ films was determined by CV measurements on MOS structures.
Journal ArticleDOI
Flatband Conditions Observed for Lanthanide-Silicide Monolayers on n-Type Si(111)
Journal ArticleDOI
Conduction mechanisms in erbium silicide Schottky diodes
M. H. Unewisse,John W. V. Storey +1 more
TL;DR: In this article, the flat-band saturation current (Isf) was defined and the flatband barrier height was shown to remain constant over the entire temperature range and the Fermi level was demonstrated to be pinned to the conduction band.
Journal ArticleDOI
Determination of built-in field by applying fast Fourier transform to the photoreflectance of surface-intrinsic n+-type doped GaAs
TL;DR: In this article, the built-in electric field strength was determined at a larger power densities of a pump beam by using fast Fourier transform (FFT) techniques, where the pump was kept below 10 μW/cm2 in order to reduce the photovoltaic effects.
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Overview and status of metal S/D Schottky-barrier MOSFET technology
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