Journal ArticleDOI
Speeding up an integer-N PLL by controlling the loop filter charge
Juha Häkkinen,Juha Kostamovaara +1 more
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TLDR
This paper studies a group of methods designed to speed-up the frequency step response of integer-N phase-locked loops (PLLs) and introduces a considerably simpler waveform based on the use of two current pulses.Abstract:
This paper studies a group of methods designed to speed-up the frequency step response of integer-N phase-locked loops (PLLs). The methods are based on current signals connected to the loop filter. Optimal speed-up waveforms are found mathematically using a linear PLL model. The paper also discusses problems associated with this theoretical waveform and introduces a considerably simpler waveform based on the use of two current pulses. This method uses excess output frequency to quickly cancel the accumulated phase error. In order to accelerate the decay of the phase error, the PLL is first overdriven at the beginning of the frequency transition with an external charge pulse to the loop filter. As the phase error goes rapidly to zero, the frequency error is also reduced to zero by another charge pulse. The theory presented here is verified by measurements using a practical RF synthesizer.read more
Citations
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Journal ArticleDOI
A Robust Phase-Locked Loop Algorithm to Synchronize Static-Power Converters With Polluted AC Systems
TL;DR: A phase-locked loop algorithm appropriated for digital-signal-processor-based control implementations, where the operation of a static-power converter needs to be synchronized with an ac network, is presented.
Journal ArticleDOI
A “Flying-Adder” On-Chip Frequency Generator for Complex SoC Environment
TL;DR: A ldquoflying-adderrdquo architecture based PLL (FAPLL) is constructed, which is instantiated multiple times in this SoC for different functions, resulting in significant chip cost reduction.
Proceedings ArticleDOI
A fast locking charge-pump PLL with adaptive bandwidth
TL;DR: Design of bandwidth adaptive phase-locked loops (PLL) to achieve fast locking is presented and the measured results show that the experimental chip has properties of fast locking less than 4 mus and low power consumption about 18mW.
Journal ArticleDOI
A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor
TL;DR: A digital-control adaptive phase-locked loop with a digital locking-in monitor (LIM) consisting of a time-to-digital converter (TDC) and a bandwidth control unit (BCU) is proposed to reduce the locking time as well as to suppress the jitter when locked.
Synthesis of phase-locked loop : analytical methods and simulation
TL;DR: A general approach for analytical calculation of phase detector characteristic for classical phase-locked loop for various signal waveforms is proposed, thereby significantly reducing time required for numerical simulation of PLL.
References
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Journal ArticleDOI
Fast settling PLL frequency synthesizer utilizing the frequency detector method speedup circuit
TL;DR: From the experimental results, it is observed that fast frequency settling can be achieved and a shortcut lowpass filter (LPF) method with the FDMSC in the PLL frequency synthesizer is proposed.
Journal ArticleDOI
Pump current modulated charge pump PLL
A. Hati,Bishnu Charan Sarkar +1 more
TL;DR: It has been observed that the process of pump current 'modulation' may be used to enhance the transient behaviour of the CP-PLL.
Journal ArticleDOI
PLL synthesizer with multi-programmable divider and multi-phase detector
TL;DR: Dividers in PLL frequency synthesizers are reduced by half with multi-programmable dividers by introducing the (N+1/2) one, which has faster lock-up time and no drawbacks.
Journal ArticleDOI
A new PLL frequency synthesizer using multi-programmable divider
TL;DR: A new phase locked loop (PLL) frequency synthesizer utilizing the multiprogrammable divider which can attain a higher speed lock-up time by increasing the loop gain is proposed.
Proceedings ArticleDOI
High speed PLL frequency synthesizer with synchronous frequency sweep
TL;DR: A technique for achieving high switching speed of the phase locked loop circuits is introduced and a pretuned signal is used that helps the PLL to reach the steady state condition in a relatively short time.