Proceedings ArticleDOI
Subthreshold leakage modeling and reduction techniques [IC CAD tools]
James Kao,S. Narendra,A. Chandrakasan +2 more
- pp 141-148
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TLDR
Techniques to model subthreshold leakage currents at the device, circuit, and system levels and ways to reduce total active power by limiting leakage currents and optimally trading off between dynamic and leakage power components are explored.Abstract:
As technology scales, subthreshold leakage currents grow exponentially and become an increasingly large component of total power dissipation. CAD tools to help model and manage subthreshold leakage currents will be needed for developing ultra low power and high performance integrated circuits. This paper gives an overview of current research to control leakage currents, with an emphasis on areas where CAD improvements will be needed. The first part of the paper explores techniques to model subthreshold leakage currents at the device, circuit, and system levels. Next, circuit techniques such as source biasing, dual V/sub t/ partitioning, MTCMOS, and VTCMOS are described. These techniques reduce leakage currents during standby states and minimize power consumption. This paper also explores ways to reduce total active power by limiting leakage currents and optimally trading off between dynamic and leakage power components.read more
Citations
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Proceedings ArticleDOI
On-Chip Stochastic Communication
Tudor Dumitras,Radu Marculescu +1 more
TL;DR: This paper introduces a new communication paradigm for SoCs, namely stochastic communication, which not only separates communication from computation, but also provides the required built-in fault-tolerance to DSM failures, is scalable and cheap to implement.
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Review of Circuit Level Leakage Minimization Techniques in CMOS VLSI Circuits
Rohit Lorenzo,Saurabh Chaudhury +1 more
TL;DR: A general review of the state-of-the-art circuit level leakage minimization techniques since 1995 is presented and conceptually classifies the different techniques for leaking power dissipation.
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Power dissipation sources and possible control techniques in ultra deep submicron CMOS technologies
N. Ekekwe,Ralph Etienne-Cummings +1 more
TL;DR: An overview of the sources of the power dissipation mechanisms in the UDSM technologies, and the device and circuit techniques to control them is presented.
Proceedings ArticleDOI
Leakage-and crosstalk-aware bus encoding for total power reduction
TL;DR: This paper introduces a new buffer design approach with selective use of high threshold voltage transistors and couple this buffer design with a novel bus encoding scheme that significantly reduces total power and runtime leakage power while also eliminating capacitive crosstalk.
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McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations
TL;DR: This paper presents a multicore power, area, and timing (McPAT)-PVT, an integrated framework for the simulation of power, delay, as well as PVT variations of FinFET-based processors, based on macromodels derived from very accurate TCAD device simulations.
References
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Journal ArticleDOI
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
TL;DR: In this article, a multithreshold-voltage CMOS (MTCMOS) based low-power digital circuit with 0.1-V power supply high-speed low power digital circuit technology was proposed, which has brought about logic gate characteristics of a 1.7ns propagation delay time and 0.3/spl mu/W/MHz/gate power dissipation with a standard load.
Journal ArticleDOI
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
James W. Tschanz,James Kao,Siva G. Narendra,Rajendran Nair,Dimitri A. Antoniadis,Anantha P. Chandrakasan,Vivek De +6 more
TL;DR: Bidirectional adaptive body bias (ABB) is used to compensate for die-to-die parameter variations by applying an optimum pMOS and nMOS body bias voltage to each die which maximizes the die frequency subject to a power constraint as mentioned in this paper.
Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage
James W. Tschanz,James Kao,Siva G. Narendra,Rajendran Nair,Dimitri A. Antoniadis,Anantha P. Chandrakasan,Vivek De +6 more
TL;DR: Measurements on a 150 nm CMOS test chip show that on-chip bidirectional adaptive body biasing compensates effectively for die-to-die parameter variation to meet both frequency and leakage requirements.
Proceedings ArticleDOI
JouleTrack: a web based tool for software energy profiling
A. Sinha,Anantha P. Chandrakasan +1 more
TL;DR: A software energy estimation methodology is presented that avoids explicit characterization of instruction energy consumption and pre-dicts energy consumption to within 3% accuracy for a set of bench-mark programs evaluated on the StrongARM SA-1100 and Hitachi SH-4 microprocessors.
Proceedings ArticleDOI
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks
TL;DR: Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.