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Transactions on Power Electronics
IEEE TRANSACTIONS ON POWER ELECTRONICS
Yanfeng Shen, Member, IEEE, Huai Wang, Senior Member, IEEE, Frede Blaabjerg, Fellow, IEEE,
Hui Zhao, Member, IEEE, and Teng Long, Member, IEEE
Abstract— Miniature power semiconductor devices mounted on
printed circuit boards (PCBs) are normally cooled by means of
PCB vias, copper pads, and/or heatsinks. Various reference PCB
thermal designs have been provided by semiconductor
manufacturers and researchers. However, the recommendations
are not optimal, and there are some discrepancies among them,
which may confuse electrical engineers. This paper aims to develop
analytical thermal resistance models for PCB vias and pads, and
further to obtain the optimal design for thermal resistance
minimization. Firstly, the PCB via array is thermally modeled in
terms of multiple design parameters. A systematic parametric
analysis leads to an optimal trajectory for the via diameter at
different PCB specifications. Then an axisymmetric thermal
resistance model is developed for PCB thermal pads where the
heat conduction, convection and radiation all exist; due to the
interdependence between the conductive/radiative heat transfer
coefficients and the board temperatures, an algorithm is proposed
to fast obtain the board-ambient thermal resistance and to predict
the semiconductor junction temperature. Finally, the proposed
thermal models and design optimization algorithms are verified by
computational fluid dynamics (CFD) simulations and
experimental measurements.
Index terms— thermal resistance model, thermal management,
printed circuit board (PCB), PCB via, thermal pad.
NOMENCLATURE
Bi Biot number
h Heat transfer coefficient (W/(m
2
·K))
h
conv
Convective heat transfer coefficient (W/(m
2
·K))
h
radi
Radiative heat transfer coefficient (W/(m
2
·K))
k Thermal conductivity of a material (W/(m·K))
k
1
Lateral thermal conductivity of the copper zone
(W/(m
2
·K))
k
2
Lateral thermal conductivity of the FR4 zone
(W/(m
2
·K))
k
Cu
Thermal conductivity of copper (W/(m
2
·K))
k
FR4
Thermal conductivity of FR4 (W/(m
2
·K))
k
filler
Thermal conductivity of via filling material (W/(m
2
·K))
l Length of a via array (m)
L
c
Characteristic length of a hot plate (m)
m
1
Number of rows of a via array in Pattern I
m
2
Number of rows of a via array in Pattern II
n
1
Number of columns of a via array in Pattern I
n
2
Number of columns of a via array in Pattern II
N
Cu
Number of copper layers in a PCB
P Power loss generated by a heat source (W)
q Heat flux (W/m
2
)
r
b
Radius of heat source (package) (m)
r
s
Radius of middle (copper) zone (m)
r
e
Radius of outer (FR4) zone (m)
s Via-to-via spacing (m)
t PCB thickness(m)
t
Cu
Thickness of a PCB copper layer (m)
t
PTH
Plating thickness of PCB vias (m)
T
b
PCB board (r = r
b
) temperature (
o
C)
T
c
Case temperature of a package (chip) (
o
C)
T
j
Junction temperature of a chip (
o
C)
T
t
Top case temperature of a package (chip) (
o
C)
T
a
Ambient temperature (
o
C)
w Width of a via array (m)
Emissivity of PCB surface
ba
Thermal resistance from the inner zone edge (r = r
b
) to
the ambient (
o
C/W)
barrel
Vertical thermal resistance of the copper barrel in a via
unit (
o
C/W)
cb
Thermal resistance from the case to the PCB (r = r
b
)
(
o
C/W)
unit
Vertical thermal resistance of a via unit (
o
C/W)
Cu
Vertical thermal resistance of the copper layers in a via
unit (
o
C/W)
filler
Vertical thermal resistance of the filler in a via unit
(
o
C/W)
FR4
Vertical thermal resistance of the FR4 layers in a via
unit (
o
C/W)
jc
Thermal resistance from the junction to the case (
o
C/W)
jt
Thermal resistance from the junction to the top case
(
o
C/W)
r,ij
Radial thermal resistance between outer-zone via layers
(
o
C/W)
sa
Thermal resistance from the copper zone edge (r = r
s
)
to the ambient (
o
C/W)
Thermal Modeling and Design Optimization of
PCB Vias and Pads
Part of this work was presented at the 10
th
IEEE Energy Conversion
Congress & Expo (ECCE2018), Portland, USA, and the 29
th
European
Symposium on Reliability of Electron Devices, Failure Physics and
Analysis (ESREF2018), Aalborg, Denmark. This work was supported
by the Innovation Fund Denmark through the Advanced Power
Electronic Technology and Tools (APETT) project. (Corresponding
authors: Teng Long and Yanfeng Shen).
Y. Shen, H. Zhao and T. Long are with the Department of
Engineering–Electrical Engineering Division, University of
Cambridge, Cambridge CB3 0FA, United Kingdom (e-mail:
ys523@cam.ac.uk, hz352@cam.ac.uk, tl322@cam.ac.uk)
H. Wang, and F. Blaabjerg are with the Center of Reliable Power
Electronics (CORPE), Department of Energy Technology, Aalborg
University, Aalborg 9220, Denmark (e-mail: hwa@et.aau.dk,
fbl@et.aau.dk).
0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2915029, IEEE
Transactions on Power Electronics
ta
Thermal resistance from the top case of the chip to the
ambient (
o
C/W)
via
Vertical thermal resistance of a via array (
o
C/W)
via,n
Normalized vertical thermal resistance of a via array
v,ij
Vertical thermal resistance between copper layers of
outer-zone vias (
o
C/W)
Convective heat transfer parameter depending on PCB
geometry and orientation
Stefan-Boltzmann constant
= 5.670367×10
−8
(W⋅m
−2
⋅K
−4
)
Time (s)
Via diameter (m)
opt
Optimal via diameter (m)
ea
Equivalent thermal resistance from the FR4 zone edge
(r = r
e
) to the ambient (
o
C/W)
sa
Equivalent thermal resistance from the copper zone
edge (r = r
s
) to the ambient (
o
C/W)
ta
Equivalent thermal resistance from the top case of a
package to the ambient (
o
C/W)
I. INTRODUCTION
The volume of modern power semiconductor devices (e.g.,
GaN transistors) are continuingly shrinking in order to achieve
higher power densities, lower parasitic inductances, and lower
power losses [1]-[3]. However, thermal management has been
identified as the main barrier for further power density increase
[4]. The heat generated inside the miniaturized semiconductors
must be effectively dissipated to the ambient; otherwise, the
high junction and board temperatures may cause serious
reliability issues to the semiconductor, solder, thermal grease,
and printed circuit board (PCB) [5]-[8]. In addition, suitable
heat dissipation measures should be considered as early as in
the design and development phase, because subsequent
modifications are generally more costly and involve increased
engineering effort [9], [10].
In medium power applications, the surface-mounted devices
(SMDs) are normally cooled by a heatsink attached to the PCB,
where the thermal via array provides an effective thermal path
for the heat transfer [11]-[13]. In low power scenarios, a PCB
copper pad is typically used for heat spreading, and the SMD
can be cooled by natural convection [14]. Many reference
thermal designs can be found from device manufacturers’
websites [14]-[18]. However, several problems remain:
1) the thermal design guidelines recommended by
manufacturers are not optimal, and they are applicable for
specific packages only [15], [16];
2) inconsistent guidelines; for instance, the thermal via
diameter should be designed as large to reduce the thermal
resistance according to [16]; however, [15], [17] and [18]
recommend smaller via diameters and adopt different via
pitches.
Although the computational fluid dynamics (CFD)
simulations feature high accuracy, the model generation time
and computational cost could be fairly high [14]. Moreover,
CFD simulators are expensive and they are not always available
for electrical engineers. Therefore, it is necessary to develop
analytical models which enable fast and accurate design
optimization for thermal vias and pads.
In the literature, many efforts have been devoted to the
optimization of PCB thermal vias. The research in [19]-[21] is
based on either experimental results or CFD simulations; thus,
not all design scenarios are explored, but only some general
design guidelines are provided for specific applications.
Analytical thermal models of vias are built in [11], [22]-[25];
unfortunately, only partial parameters are analyzed, and no
optimal via design is derived.
For the PCB heat transfer characteristics, the heat conduction,
convection and radiation all exist, which makes the thermal
analysis complicated. Texas Instruments have developed an
online PCB thermal calculation tool based on CFD thermal
resistance data of different package sizes and pad dimensions
[26]. However, some important factors (e.g., the PCB thickness,
number of copper layers, and copper thickness) are not taken
into account, and also the online tool does not support design
optimization. In addition to the CFD simulations, some other
numerical calculation methods are developed [27], [28]. The
study in [28] deals with a substrate for a ball grid array package,
where a belt of densely populated vias and two continuous
copper layers are placed; however, the model is complicated
and no CFD or experimental verifications are provided. For
electrical engineers, it is more desirable to have an analytical
thermal model such that the temperatures of devices with
different designs and cooling methods can be fast predicted [29],
[30]. In [14] and [31], an analytical thermal resistance model is
developed for PCB thermal pads; however, the heat transfer
boundary and the convective heat transfer coefficient variation
over the temperature difference are not included, causing
potential errors between calculations and measurements.
This paper proposed two new analytical thermal models for
PCB vias and thermal pads, respectively. For the thermal model
of PCB vias, a systematic parametric analysis is firstly
conducted, which leads to a simplified thermal resistance model.
An optimal design trajectory is then obtained for PCB vias with
different specifications. After that, an analytical axisymmetric
thermal resistance model is proposed for PCB thermal pads.
Taking into account the interdependence between the
convection/radiative heat transfer coefficients and board
temperatures, a simple algorithm is developed to size thermal
pads at different PCB parameters, power losses, ambient
temperatures, and allowed maximum junction temperatures.
Finally, CFD simulations and experimental measurements
verify the developed analytical thermal models. The proposed
models enable electrical engineers to optimize their PCB via
design and thermal pad sizing at lower cost and less time effort.
II. THERMAL MODELING AND DESIGN OPTIMIZATION OF PCB
VIAS
A. Thermal Modeling of PCB Vias
A cluster of PCB plated through holes (PTHs), i.e., vias, can
provide an effective thermal path, which helps to transfer heat
from an SMD (chip) to a heatsink. The vertical structure of a
multilayer PCB with vias is shown in Fig. 1(a). The via
diameter, via-to-via spacing, and via plating thickness are
denoted as
, s, and t
PTH
, respectively. The number of copper
layers and the copper layer thickness are represented by N
Cu
and
t
Cu
, respectively.
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Transactions on Power Electronics
For the layout of vias, there are various uniform and non-
uniform design options. For the sake of simplicity, this paper
focuses on two simple uniform patterns, denoted as Pattern I
and Pattern II, as illustrated in Fig. 1(b) and (c), respectively.
However, the derived method can be applied to other vias
layout with minor modifications. The length, width, and
thickness of the PCB via array are denoted as l, w, and t,
respectively. Normally, the PCB thickness is much smaller than
its length and width. Also, the attached heatsink has a large heat
dissipation capability. Therefore, it is assumed that the heat
generated inside the SMD is transferred in the vertical direction
only. Accordingly, the PCB via array in each pattern can be
divided into multiple via units, as indicated by the dashed box
in Fig. 1. It is seen from the horizontal cross-sections of the via
array that the basic via unit in Pattern I is a square of (
+ s) ×
(
+ s), whereas that in Pattern II is rectangular with [
√
3(
+
s)/2] × (
+ s). If the PCB via array size (l and w) and via
parameters (
and s) are fixed, and the array parameters (l and
w) are much larger than the via unit parameters (
and s), then
the numbers of vias that Patterns I and II can accommodate are
calculated as
11
22
2
2
floor[ / ( )] floor[ / ( )]
/ [( ], Pattern I
floor[ / ( )] floor{2 / [ 3( ]}
2 / [ 3( ], Pattern I
)
)
) I
m n l w
lw
m n l w
l
ss
s
s
w
s
s
(1)
It is seen from (1) that Pattern II can accommodate
approximately
2 / 3 1
= 15.5% more vias than Pattern I.
As can be seen from Fig. 1, there are three vertical thermal
paths for each via unit, i.e., the via filler, the via barrel, and the
copper and flame retardant 4 (FR4) layers, whose vertical
thermal resistances are represented by
barrel
,
filler
, and
Cu
+
FR4
, respectively, as below
2
4
22
2
4
2
,
( / 2
,
(
1
,
)
)
)
)
Pattern I
( / 4
1
, Pattern II
3/2(4/
filler
filler
barrel
Cu
Cu Cu Cu Cu
C
PTH
PTH PTH
Cu FR
u FR
t
kt
t
k t t
N t t N t
kk
s
s
(2)
t
Cu
t
FR4
t
s
(a)
FR4
Copper layer
Filler
Chip
Solder
PCB
TIM
Heatsink
t
PTH
s
t
PTH
s
...
...
...
...
...
...
...
...
× n
1
× m
1
+ s
+ s
l
w
(b)
...
...
...
...
+ s
+ s
s
s
s
+ s
3( ) / 2s
...
...
...
×n
2
×m
2
l
w
(c)
+ s
Via unit
Via unit
Via unit
+ s
filler
FR4
+
Cu
barrel
Fig. 1. Structure and layout of PCB via array. (a) Vertical structure of a
multilayer PCB with vias. Top view of via array in (b) Pattern I and (c) Pattern
II.
where k
filler
, k
Cu
and k
FR4
represent the thermal conductivities of
via filling material, copper, and FR4, respectively. Thus, the
vertical thermal resistance of a via unit can be calculated as
4
4
,
2
22
1/ 1/
1
4
/( )
|| || ( )
1
( / 2
(
( / 4
/ ( ) /
)
)
)
filler barrel
Cu FR
PTH
P
unit filler barrel Cu FR
unit I
filler
Cu TH PTH
Cu FRCu Cu Cu Cu
kt
k t t
t t N t k t N t k
s
4
,
2
4
22
1/ 1/
1/( )
, Pattern I
1
( / 2
(
3( / 4
/
)
)
) / 2
( ) /
filler barrel
Cu FR
unit II
filler
Cu
C
PTH
uC
PTH PTH
Cu Fu Cu Cu R
kt
k t t
t t N t k t N t k
s
, Pattern II
(3)
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Transactions on Power Electronics
From the perspective of vertical heat transfer, the via units are equivalently connected in parallel, and therefore the total
vertical thermal resistances of a via array of l w t can be obtained as
,
11
,
22
, Pattern I
, Pattern II
unit I
via
unit II
mn
mn
(4)
To simplify the following theoretical analysis, the thermal resistance of a via array is normalized based on the thermal
resistance of an FR4 pad with the same size (l w t), yielding (5).
4
2
4
22
2
4
,
4
]
))
/ ) /
4( )
[4 8 (4 )
( 2 4 (
(
PTH PTH PTH
Cu Cu Cu
c
FR
filler Cu
Cu Cu FR
barr
opper and FR layer
el
fi
s
ller
via
via n
FR
sk
t s s
k t k t t
N t t N t k
t
k lw
k
2
4
22
2
4
4
, Pattern I
2 3( )
[2 3( ) ]
))
//
( 2 4 (
( )
FR
filler Cu
Cu Cu FR
barre
PTH PTH PTH
Cu Cu Cu
copper and F
l
fill
Rl
er
ayers
sk
ts
k t k t t
N t t N t kk
, Pattern II
(5)
B. Parametric Analysis and Design Optimization of PCB
Vias
TABLE I
THERMAL CONDUCTIVITIES OF MATERIALS AT 25
O
C [33]-[36]
Material
Copper
SnAgCu
solder
FR4
Air at
atmospheric
pressure
Through-
plan
In-plane
Thermal
conductivity
393
W/(mK)
57.3
W/(mK)
0.29
W/(mK)
0.81
W/(mK)
0.026
W/(mK)
Since multiple design variables are included in the thermal
resistance model, it is difficult to directly apply (5) in
practical design optimization. Hence, it is necessary to
conduct a parametric analysis on (5).
The thermal conductivity of a material is a measure of its
ability to conduct heat. It is evaluated primarily in terms of
the Fourier’s law for heat conduction. The general equation
for thermal conductivity is [32]
/k q T
, where q is
the heat flux (W/m
2
) and
T
represents the temperature
gradient (K/m). The thermal conductivities of the materials
used in this paper are listed in Table I. The standard IPC-
6012 specifies a minimum copper plating thickness of 20 µm
for Class 1 PCBs, and 25 µm is a standard via plating
thickness [37]. Thus, t
PTH
= 25 µm is used in the following
analysis.
1) Via-to-Via Spacing s
Based on (5), the curves of the normalized via thermal
resistance with respect to the via-to-via spacing s can be
depicted for different filler materials, PCB thicknesses, and
via diameters, as shown in Fig. 2. It is seen that the
normalized via thermal resistance
via,n
always rises when
the via-to-via spacing s increases, regardless of the PCB
thickness, via filling material and via diameter. Therefore, s
should be designed as small as possible in order to reduce the
thermal resistance of PCB via array. In practice, however,
the allowed minimum via-to-via spacing depends on PCB
manufacturing capability and is cost sensitive. Generally, 8
mil (0.2 mm) is a commonly-specified minimum via-to-via
spacing by most PCB manufacturers, and therefore, s = 0.2
mm is used in the following analysis and experiments.
t = 0.6 mm
t = 1 mm
t = 1.6 mm
= 1 mm
= 0.1 mm
= 0.5 mm
= 0.2 mm
(a)
t = 0.6 mm
t = 1 mm
t = 1.6 mm
= 1 mm
= 0.1 mm
= 0.5 mm
= 0.2 mm
(b)
Via-to-via spacing s (m)
Via-to-via spacing s (m)
Fig. 2. Dependence of the normalized thermal resistance of via array in
Pattern I on the via-to-via spacing s with two via filling materials: (a) air
with a thermal conductivity of 0.026 W/(mK), and (b) solder with a thermal
conductivity of 57.3 W/(mK).
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Transactions on Power Electronics
= 1 mm
= 0.1 mm
= 0.5 mm
= 0.2 mm
= 1 mm
= 0.1 mm
= 0.5 mm
= 0.2 mm
= 1 mm
= 0.1 mm
= 0.5 mm
= 0.2 mm
= 1 mm
= 0.1 mm
= 0.5 mm
= 0.2 mm
= 1 mm
= 0.1 mm
= 0.5 mm
= 0.2 mm
= 1 mm
= 0.1 mm
= 0.5 mm
= 0.2 mm
0.5 oz, t
l
= 17.5 mm
1 oz, t
l
= 35 mm
0.5 oz, t
l
= 17.5 mm
1 oz, t
l
= 35 mm
0.5 oz, t
l
= 17.5 mm
1 oz, t
l
= 35 mm
2 oz, t
l
= 70 mm
0.5 oz, t
l
= 17.5 mm
1 oz, t
l
= 35 mm
2 oz, t
l
= 70 mm
0.5 oz, t
l
= 17.5 mm
1 oz, t
l
= 35 mm
2 oz, t
l
= 70 mm
0.5 oz, t
l
= 17.5 mm
1 oz, t
l
= 35 mm
2 oz, t
l
= 70 mm
t t t
tt
t
(a) (b) (c)
(d) (e) (f)
N
Cu
N
Cu
N
Cu
N
Cu
N
Cu
N
Cu
t
Cu
t
Cu
t
Cu
t
Cu
t
Cu
t
Cu
t
Cu
t
Cu
t
Cu
t
Cu
t
Cu
t
Cu
t
Cu
t
Cu
t
Cu
t
Cu
0.026
6
0.026
0.026
Fig. 3. Dependence of the normalized thermal resistance of via array in Pattern I on the number of copper layers N
Cu
, copper thickness t
Cu
, and PCB thickness
t with different via filling materials. (a) Air with thermal conductivity k
filler
= 0.026 W(mK) and PCB thickness t = 0.6 mm; (b) Air with thermal conductivity
k
filler
= 0.026 W(mK), PCB thickness t = 1.0 mm; (c) Air with thermal conductivity k
filler
= 0.026 W(mK), PCB thickness t = 1.6 mm; (d) Solder with thermal
conductivity k
filler
= 57.3 W(mK), PCB thickness t = 0.6 mm; (e) Solder with thermal conductivity k
filler
= 57.3 W(mK), PCB thickness t = 1.0 mm; (f) Solder
with thermal conductivity k
filler
= 57.3 W(mK), PCB thickness t = 1.6 mm.
×10
-3
×10
-3
t = 1.6 mm
t = 0.4 mm
k
filler
=0.026W/(mK)
k
filler
=0.35W/(mK)
k
filler
=20W/(mK)
k
filler
= 57.3 W/(mK)
t = 1.6 mm
t = 0.4 mm
Minima
trajectory
s
k
filler
=0.026W/(mK)
k
filler
=0.35W/(mK)
k
filler
=20W/(mK)
k
filler
= 57.3 W/(mK)
Minima
trajectory
(a) (b) (c)
Via diameter Via diameter
s
Fig. 4. (a) Optimal trajectories of via diameter
and via-to-via spacing s with respect to the filler thermal conductivity. Dependence of the normalized
thermal resistance of via array on the diameter
at different PCB thicknesses and filler thermal conductivities for (b) Pattern I and (c) Pattern II.
2) Number of layers N
Cu
, PCB Thickness t, and Copper
Layer Thickness t
Cu
The dependence of the normalized thermal resistance of a
PCB via array,
via,n
, on the number of copper layers N
Cu
,
copper thickness t
Cu
, and PCB thickness t is shown in Fig. 3.
As can be seen, the parameters N
Cu
, t
Cu
and t, have a
negligible impact on the normalized thermal resistance,
implying that the copper and FR4 layers have a much higher
thermal resistance compared to the vias. Thus the heat is
mainly transferred through the vias, and (5) can be simplified
as
2
4
2
,
2
4
2
4( )
,
4 ( ( 2
2 3( )
,
4 ( () 2
))
)
FR
Cu filler
via n
F
PTH PTH PTH
PTH PTH
R
Cu fille PTHr
sk
k t t k t
Pattern I
sk
k t t k t
Pattern II
(6)
