Showing papers on "Analog-to-digital converter published in 2004"

Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter

Abstract: Offset mismatch, gain mismatch, and sample-time error between time-interleaved channels limit the performance of time-interleaved analog-to-digital converters (ADCs). This paper focuses on the sample-time error. Techniques for correcting and detecting sample-time error in a two-channel ADC are described, and simulation results are presented.

A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration

Abstract: This paper presents a prototype analog-to-digital converter (ADC) that uses a calibration algorithm to adaptively overcome constant closed-loop gain errors, closed-loop gain variation, and slew-rate limiting. The prototype consists of an input sample-and-hold amplifier (SHA) that can serve as a calibration queue, a 12-bit 80-MSample/s pipelined ADC, a digital-to-analog converter (DAC) for calibration, and an embedded custom microprocessor, which carries out the calibration algorithm. The calibration is bootstrapped in the sense that the DAC is used to calibrate the ADC, and the ADC is used to calibrate the DAC. With foreground calibration, test results show that the peak differential nonlinearity (DNL) is -0.09 least significant bits (LSB), and the peak integral nonlinearity (INL) is -0.24LSB. Also, the maximum signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 71.0 and 79.6dB with a 40-MHz sinusoidal input, respectively. The prototype occupies 22.6 mm/sup 2/ in a 0.25-/spl mu/m CMOS technology and dissipates 755 mW from a 2.5-V supply.

A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

Abstract: A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free dynamic range (SFDR) of 93.3 dB, a total harmonic distortion (THD) of -92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm/sup 2/ in 0.35-/spl mu/m CMOS.

A system and method for excluding narrow band noise from a communication channel

Abstract: A signal filtering system and method that may be used in conjunction with a repeater or an input stage of a base-station. The system may include an analog to digital converter adapted to sample a received signal and to produce a data stream corresponding to the received signal in the time domain, a filtering block having one or more digital filter elements, wherein each of said one or more filter elements is adapted to filter one or more sets of frequency bands associated with one or more communication channel, and a controller adapted to configure said one or more digital filter elements based on parameters stored on a database and/or based on parameters received via a modem.

Method and apparatus for authenticating a magnetic fingerprint signal using an adaptive analog to digital converter

Abstract: A system for verifying the authenticity of data contained in a magnetic medium using the remanent noise characteristics of the magnetic medium. One embodiment of the invention includes an over-sampled modulator and at least one channel in communication with an output of the over-sampled modulator. The at least one channel is configured to filter the output of the over-sampled modulator and the at least one channel is configured to vary the bandwidth of the filter applied to the output of the over-sampled modulator in response to variations in the bandwidth of the signal generated by the sensing unit.

The DRS chip: Cheap waveform digitizing in the GHz range

Abstract: An analog sampling chip is currently under development for fast waveform digitizing of PMT and drift chamber signals for the MEG Experiment at PSI. This experiment searches for the lepton-flavour violating decay μ + →e + γ with a sensitivity down to 10 −13 . The first prototype of the chip contains 768 capacitive sampling cells fabricated in a 0.25 μm CMOS process. Sampling takes place with an on-chip generated frequency ranging up to 2.5 GHz. The cells are read out at 40 MHz with an external 12 bit flash ADC. The design of the chip is described and test results from the first prototype are reported.

Systems and methods for power conservation in a CMOS imager

Abstract: The present invention provides systems and methods capable of reducing power consumption in an imaging device. One imaging device includes two analog to digital converters that are separately programmable and can be in different power modes. Each analog to digital converter is capable of creating an image derived from a pixel array that has a full field of view, but lower resolution.

Low kickback noise techniques for CMOS latched comparators

Abstract: The latched comparator is utilized in virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. Such high voltage variations in the regeneration nodes are coupled to the input voltage - kickback noise. This paper reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations verify the effectiveness of our techniques.

Integrated radio circuit having multiple function I/O modules

Abstract: An integrated radio circuit includes a receiver section, a transmitter section, an analog to digital converter section, a digital to analog converter section, a digital baseband processing module, a first dual function input/output (I/O) module, and a second dual function I/O module. The first dual function input/output (I/O) module is operably coupled to provide inbound digital baseband signals as selected inbound digital baseband signals to the digital baseband processing module when the integrated radio circuit is in a normal mode of operation and to provide test inbound digital baseband signals as the selected inbound digital baseband signals to the digital baseband processing module when the integrated radio circuit is in a test mode. The second dual function I/O module is operably coupled to provide outbound digital baseband signals to the digital to analog converter section when the integrated radio circuit is in the normal mode of operation and to output the outbound digital baseband signals when the integrated radio circuit is in the test mode.

Position-sensitive Si pad detectors for electron emission channeling experiments

Abstract: Position-sensitive detector systems, initially developed for the detection of X-rays, have been adapted for their use in electron emission channeling experiments. Each detection system consists of a 30.8×30.8 mm 2 22×22-pad Si detector, either of 0.3, 0.5 or 1 mm thickness, four 128-channel preamplifier chips, a backplane trigger circuit, a sampling analog to digital converter, a digital signal processor, and a personal computer for data display and storage. The operational principle of these detection systems is described, and characteristic features such as energy and position resolution and maximum count rate, which have been determined from tests with conversion electrons and β − particles in the energy range 40–600 keV, are presented.

A baseband processor for pulsed ultra-wideband signals

Abstract: This paper presents a baseband processor for pulsed ultrawideband signals. It consists of an analog to digital converter (ADC), a clock generation system and a digital back-end. The FLASH interleaved ADC provides four bit samples at 1.2 GSPS. The back-end uses parallelization to process these samples and to reduce the signal acquisition time to 70 /spl mu/s. The baseband processor was implemented in the same 0.18 /spl mu/m CMOS chip as a part of a complete transceiver. A complete 193 kbps wireless link is demonstrated.

Characterization of a High-Resolution Analog-to-Digital Converter with an Ac Josephson Voltage Source

Abstract: A Josephson AC voltage source was employed to characterize the dynamic behavior of a high-resolution 28-bit (8.5-digit) integrating analog-to-digital converter of a digital sampling voltmeter (DSV), which is widely used in AC metrology at the Physikalisch-Technische Bundesanstalt. Extensive measurements were carried out to validate previous mathematical models of the DSV when sampling AC signals. The characterization method is based on the discrete Fourier transform applied on sampled data of the ADC and on the known Josephson plateau values for quantifying the ratio of AC quantities and the nonlinearities of the DSV. The method shown allows considerable improvement of the accuracy of sampling techniques at low frequencies (DC up to some kilohertz) to be attained.

A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching

Abstract: This work describes a 10-b multibit-per-stage pipelined CMOS analog-to-digital converter (ADC) incorporating the merged-capacitor switching (MCS) technique. The proposed MCS technique improves the signal processing speed and resolution of the ADC by reducing the required number of unit capacitors by half in comparison to a conventional ADC. The ADC resolution based on the proposed MCS technique can be extended further by employing a commutated feedback-capacitor switching (CFCS) technique. The prototype ADC achieves better than 53-dB signal-to-noise-and-distortion ratio (SNDR) at 120 MSample/s and 54-dB SNDR and 68-dB spurious-free dynamic range (SFDR) for input frequencies up to Nyquist at 100 MSample/s. The measured differential and integral nonlinearities of the prototype are within /spl plusmn/0.40 LSB and /spl plusmn/0.48 LSB, respectively. The ADC fabricated in a 0.25-/spl mu/m CMOS occupies 3.6 mm/sup 2/ of active die area and consumes 208 mW under a 2.5-V power supply.

Flash adc receiver with reduced errors

Abstract: Symbol decoding errors at a receiver utilising a flash analog to digital converter (ADC) can be reduced by adjusting a reference voltage level of the ADC where a decoding error rate at the reference voltage level exceeds a threshold.

A 2.7mW 1MSps 10b analog-to-digital converter with built-in reference buffer and 1LSB accuracy programmable input ranges

Abstract: A CMOS 1 MSps 10 bit charge-redistribution SAR ADC processes single-ended signals with 1 LSB accuracy selectable input ranges up to supply voltage A new DAC architecture presents the benefits of a differential approach while sampling single-ended signals Thanks to new low power design solutions in the ADC comparator and the built-in reference buffer, the total ADC power consumption is only 27 mW at 24 V supply and 1 MSps The active area is 04 mm/sup 2/ in a 035 /spl mu/m CMOS process

An 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter in SiGe technology

Abstract: This paper deals with the design and implementation of an 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter (ADC) using a SiGe technology with a unity gain cutoff frequency f/sub T/ of 47 GHz. The high-speed high-resolution ADC has applications in direct IF sampling receivers for wideband communication systems. The converter occupies an area of 3.5 mm/spl times/3.5 mm including pads and exhibits an effective resolution bandwidth of 700 MHz at a sampling rate of 2 Gsample/s. The maximum DNL and INL are 0.5 and 1 LSB, respectively. The ADC dissipates 3.5W (including output buffers) from a 3.3-V power supply.

Online calibration of a Nyquist-rate analog-to-digital converter using output code-density histograms

Abstract: A scheme for the online correction of static nonlinearities in a Nyquist-rate analog-to-digital converter (ADC), using output code-density histograms, is presented. The estimation of the integral nonlinearity (INL) at each output level, followed by the creation of a corresponding entry in the look-up table for error correction, is analytically explained. The suitability of the scheme for calibrating high-end ADCs has been demonstrated. An extra ADC and the associated switching and postprocessing DSP circuitry along with some memory for storing the data to be processed, are the overhead in this scheme. An improvement of over 20 dB in the spurious-free dynamic range, from an uncalibrated value of over 80 dB, has been achieved.

Channelized analog-to-digital converter

Abstract: A waveform acquisition system that captures and digitizes a wideband electrical signal through a bank of front end filters, frequency down converters, and conventional digitizers (A/D converters). A software algorithm reconstructs the composite input signal and applies the necessary corrections to remove the effects of hardware impairments. This approach is possible because it uses a class of filters that exhibit the quality of perfect waveform reconstruction, allowing signals whose spectral components overlap multiple filter bands, to be faithfully reconstructed. A calibration generator switched into the input port serves as a reference for quantifying and removing hardware errors. The channelized analog-to-digital converter (ADC) effectively multiplies the bandwidth and sampling rate of the conventional digitizer performance in a single channel by the number of channels in the system.

Method for reducing DAC resolution in multi-bit sigma delta analog-to digital converter (ADC)

Abstract: A method for reducing the resolution of a digital-to-analog converter in a multi-bit sigma-delta ADC is described. With the addition of digital sigma-delta modulators in the feedback path of a sigma-delta ADC, the truncation errors between the digital word output of the multi-bit sigma-delta ADC to the DAC input can be shaped to higher order than that of the quantization error. Thus, the DAC resolution can be reduced and the implementation of DEM for multi-bit DAC can be avoided. A preferred embodiment comprises selecting an outermost feedback loop in a sigma-delta ADC that has not been replaced and replacing it with a circuit with an equivalent transfer function. The circuit can be further enhanced with an additional term if the order of the noise shaping of the circuit is less than the order of the noise shaping of the sigma-delta ADC.

Reduced chop rate analog to digital converter system and method

Abstract: A reduced chop rate analog to digital converter technique including selectively weighting input samples to a digital filter, alternately inverting the polarity of an input error into positive and negative error components; and generating the positive and negative error components in a plurality of time response intervals of the digital filter in which the sum of the weights of the positive and negative error components are substantially equal.

Analog to digital converter

Abstract: A circuit is provided for reducing mismatches between the outputs of successive pairs of cells in an analog to digital converter. A voltage input means is coupled to a first input terminal of each cell to introduce and an input voltage. A reference voltage means is coupled to a second input terminal of each cell to introduce progressive fractions of a reference voltage. A low impedance means is coupled between corresponding first output terminals and coupled between corresponding second output terminals in successive cells, to draw load-bearing currents to the successive cells, affecting the relative voltages and thereby reducing the effects of cell mismatches on these output terminals. Lastly, a high impedance means is coupled to the each of the first output terminals and to each of the second output terminals in successive cells.

Multiplexed-input-separated sigma-delta analog-to-digital converter design for pixel-level analog-to-digital conversion

Abstract: An image-sensing element has an array of photodiodes or other photodetecting elements and performs sigma-delta analog-to-digital conversion on the outputs of the photodetecting elements. The sigma-delta analog-to-digital converters have components divided between pixel-level and row-level structures, with each row-level structure connected to its pixel-level structures to define a multiplexed-input-separated sigma-delta analog-to-digital converter. The converter can include an integrator or can rely on an integration effect of the photodetecting element. The feedback required for sigma-delta analog-to-digital conversion can involve digital-to-analog converters located at each row-level structure or at each pixel-level structure.

Sigma-delta analog-to-digital converter (ADC) with truncation error cancellation in a multi-bit feedback digital-to-analog converter (DAC)

Abstract: A method for reducing the complexity of a multi-bit DAC in a sigma-delta ADC. The DAC resolution can be made to be less than that of the quantizer by canceling truncation error present in multi-bit DACs. Truncation errors are introduced by differences between the digital output word of the quantizer and the digital input word of the feedback DAC(s). The truncation error(s) can be cancelled and eliminated from the system transfer function. A preferred embodiment comprises expanding all feedback loops in the ADC, adding an adjusted truncation error for each feedback loop to an inner feedback loop, and then calculating a correction term for each adjusted truncation error. The correction term can be calculated by zeroing all signals except for the adjusted truncation error being canceled and then calculating a truncation error transfer function.

An analog-to-digital-converter comprising a sigma-delta-modulator and receiver with such analog-to-digital-converter

Abstract: Analog-to-digital converter including a sigma-delta modulator (SD) with noise shaping filtering. Signal transfer filtering is introduced in the feedback loop of the sigma-delta modulator. This may be done without affecting the noise shaping filtering e.g. with a signal transfer filter (L) in the forward path of the feedback loop and a complementary signal transfer path (H) in the feedback path of the loop. The analog-to-digital converter may be used for channel filtering, FM-demodulation and/or image rejection in communication receivers.

A 600MS/s, 5-bit pipelined analog-to-digital converter for serial-link applications

Abstract: Design of a high-speed low-to-medium resolution analog-to-digital converter with closed-loop pipeline structure has been investigated. We demonstrate a single-path 600MS/s, 5-bit ADC. It is optimally designed to meet the requirements of a serial-link receiver. For high input-bandwidth, total input-capacitance is only 170fF. At high frequencies, to improve resolution beyond the amplifier-settling limit, the reference voltage of each pipeline-stage is digitally tuned. The chip is fabricated in 0.18 /spl mu/m CMOS technology and consumes 70mW at 1.8V power-supply.

Analog-to-digital converter utilizing a timer for increased resolution

Abstract: An analog-to-digital converter includes a capacitor for storing charge and a current source for flowing current through the capacitor for charging the capacitor. The analog-to-digital converter also contains a switch for controlling flow of current from the current source to the capacitor, a comparator for outputting a first comparison value when an analog input voltage is approximately equal to a voltage across the capacitor, and a timer for calculating a charging period of time needed for the voltage across the capacitor to become equal to the analog input voltage. A controller is used for controlling operation of the switch, for starting the timer when the switch electrically connects the current source to the capacitor for charging the capacitor, for stopping the timer when the comparator outputs the first comparison value, and for converting the charging period of time calculated by the timer into a digital output voltage.

Calibrating a phase detector and analog-to-digital converter offset and gain

Abstract: The present invention includes apparatus and methods to calibrate a phase detector and an analog-to-digital converter (ADC) offset and gain In one such embodiment, an apparatus includes a phase detector to generate an error pulse and a reference pulse, a combiner to combine the pulses, and an ADC to receive the combined pulses, where the ADC has a full scale set by an average of the reference pulse Still further, a calibration loop may be coupled between the output of the ADC and the phase detector to generate and provide a phase adjust signal to reduce or eliminate phase offsets Other embodiments are described and claimed