Showing papers on "Analog-to-digital converter published in 2007"

Modeling of Quantization Effects in Digitally Controlled DC–DC Converters

Abstract: In digitally controlled dc-dc converters with a single voltage feedback loop, the two quantizers, namely the analog-to-digital (A/D) converter and the digital pulse-width modulator (DPWM), can cause undesirable limit-cycle oscillations. In this paper, static and dynamic models that include the quantization effects are derived and used to explain the origins of limit-cycle oscillations. In the static model, existence of dc solution, which is a necessary no-limit-cycle condition, is examined using a graphical method. Based on the generalized describing function method, the amplitude and offset-dependent gain model of a quantizer is applied to derive the dynamic system model. From the static and dynamic models, no-limit-cycle conditions associated with A/D, DPWM and compensator design criteria are derived. The conclusions are illustrated by simulation and experimental examples

VLSI Potentiostat Array With Oversampling Gain Modulation for Wide-Range Neurotransmitter Sensing

Abstract: A 16-channel current-measuring very large-scale integration (VLSI) sensor array system for highly sensitive electrochemical detection of electroactive neurotransmiters like dopamine and nitric-oxide is presented. Each channel embeds a current integrating potentiostat within a switched-capacitor first-order single-bit delta-sigma modulator implementing an incremental analog-to-digital converter. The duty-cycle modulation of current feedback in the delta-sigma loop together with variable oversampling ratio provide a programmable digital range selection of the input current spanning over six orders of magnitude from picoamperes to microamperes. The array offers 100-fA input current sensitivity at 3.4-muW power consumption per channel. The operation of the 3 mm times3 mm chip fabricated in 0.5-mum CMOS technology is demonstrated with real-time multichannel acquisition of neurotransmitter concentration

Ultra-Low-Power Interface Chip for Autonomous Capacitive Sensor Systems

Abstract: Traditionally, most of the sensor interfaces must be tailored towards a specific application. This approach results in a high recurrent design cost and time to market. On the other hand, generic sensor interface design reduces the costs and offers a handy solution for multisensor applications. This paper presents a generic sensor interface chip (GSIC), which can read out a broad range of capacitive sensors. It contains capacitance-to-voltage converters, a switched-capacitor amplifier, an analog-to-digital converter, oscillators, clock generation circuits and a reference circuit. The system combines a very low-power design with a smart energy management, which adapts the current consumption according to the accuracy and speed requirements of the application. The GSIC is used in a pressure and an acceleration monitoring system. The pressure monitoring system achieves a current drain of 2.3 muA for a 10-Hz sample frequency and an 8-bit accuracy. In the acceleration monitoring system, we measured a current of 3.3 muA for a sample frequency of 10 Hz and an accuracy of 9 bits

Analog-to-digital converter and semiconductor device

Abstract: An analog to digital converter comprising a reference signal generator, a comparator, and a counter wherein the reference signal generator is operable to generate a reference for converting an analog signal into a digital signal. The reference signal generator is also operable to generate a plurality of the reference signals based on the change in a voltage. The comparator is operable to compare the analog signal with the reference signal generated by the reference signal generator. The counter is operable to count, in parallel with a comparison performed by the comparator, a predetermined count clock and to hold a count value at the time of completion of the comparison.

A Design-Optimized Continuous-Time Delta–Sigma ADC for WLAN Applications

Abstract: A third-order continuous-time delta-sigma (DeltaSigma) analog-to-digital converter (ADC) is presented for the conversion of an input signal bandwidth of 10 MHz Design optimization towards minimal power consumption is demonstrated for the high-speed low-power building blocks of the DeltaSigma modulator From this point of view, it is shown that GmC integrators are preferred over RC integrators in the low-pass filter of the modulator because they show a better tradeoff between power, speed, and accuracy A new single-bit quantizer topology is presented that incorporates a local feedback path that improves stability using a switched-voltage technique Finally, a design methodology for the single-bit digital-to-analog converter (DAC) in the feedback loop is proposed, focusing on the impact of high sampling rates on the stability of the converter The presented continuous-time ADC achieves a simulated dynamic range of 72 dB and a signal-to-noise-and-distortion-ratio of 66 dB in a 10-MHz signal bandwidth Therefore, it can be applied for WLAN broadband communication The power consumption of the DeltaSigma modulator is limited to 75 mW The chip is designed in a 018-mum triple-well CMOS technology

Differential input successive approximation analog to digital converter with common mode rejection

Abstract: A Successive Approximation Routine converter is provided in which a comparator is responsive to an output of a first Digital to Analog Converter, and an output of a second Digital to Analog Converter and to a DAC common mode output reference voltage, and wherein the comparator provides data to a SAR controller indicating which one of the DAC outputs is greater than the other, and how a common mode voltage on the DAC outputs compares to the reference voltage. On this basis the SAR controller can add or subtract a common mode offset to the trial words being presented at a given bit trial such that both differential and common mode convergence is achieved.

Digital Controller for High-Frequency Rectifiers with Power Factor Correction Suitable for On-Chip Implementation

Abstract: This paper describes a digital controller for high-frequency single-phase power factor correction rectifiers (PFC) that is suitable for on-chip implementation. To achieve high switching frequency, fast dynamic response, and implementation with a small number of logic gates, the designs of basic functional blocks are optimized. In the outer voltage loop a windowed based analog-to-digital converter (ADC) with adjustable quantization steps is used, to achieve fast dynamic response. The complexity of the current loop realization is significantly reduced through the utilization of a floating reference created by a Sigma-Delta modulator and another windowed based ADC. In addition, a segmented ring-oscillator based digital pulse-width modulator (DPWM) is used to eliminate the need for a high frequency external clock and reduce the overall size of the system. The effectiveness of this digital architecture is demonstrated on a 200 kHz, 300 W boost-based PFC experimental prototype.

A CMOS Imager With Focal Plane Compression Using Predictive Coding

Abstract: This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit. The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizer/coder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 mum CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm times 5.96 mm which includes an 80 times 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

A Wide-Dynamic-Range CMOS Image Sensor Based on Multiple Short Exposure-Time Readout With Multiple-Resolution Column-Parallel ADC

Abstract: A wide-dynamic-range CMOS image sensor based on synthesis of one long and multiple short exposure-time signals is proposed. A high-speed, high-resolution column-parallel integration type analog-to-digital converter (ADC) with a nonlinear slope is crucial for this purpose. A prototype wide-dynamic-range CMOS image sensor that captures one long and three short exposure-time signals has been developed using 0.25-mum 1-poly 4-metal CMOS image sensor technology. The dynamic range of the prototype sensor is expanded by a factor of 121.5, compared with the case of a single long exposure time. The maximum DNL of the ADC is 0.3 least significant bits (LSB) for the single-resolution mode and 0.7 LSB for the multiresolution mode

Cystic resolution: A performance metric for ultrasound imaging systems

Abstract: This paper describes a metric that can be used to characterize the resolution of arbitrary broadband coherent imaging systems. The metric is particularly suited to medical ultrasound because it characterizes scanner performance using the contrast obtained by imaging anechoic cysts of various sizes that are embedded in a speckle-generating background, accounting for the effect of electronic noise. We present the theoretical derivation of the metric and provide simulation examples that demonstrate its utility. We use the metric to compare a low-cost, handheld, C-scan system under development in our laboratory to conventional ultrasound scanners. We also present the results of simulations that were designed to evaluate and optimize various parameters in our system, including the f/# and apodization windows. We investigate the impact of electronic noise on our system and quantify the tradeoffs associated with quantization in the analog to digital converter. Results indicate that an f/1 receive aperture combined with 10-bit precision and a signal-to-noise ratio (SNR) of 0 dB per channel would result in adequate image quality

Digital Controller for Multi-Phase DC-DC Converters with Logarithmic Current Sharing

Abstract: This paper describes a novel current-program mode digital controller and a multiphase dc-dc converter with non-uniform current sharing that optimize converter efficiency over the full range of operation. The converter phases are operated as binary-weighted constant current sources, i.e. scaled in a binary-logarithmic fashion. To minimize the system size and provide fast dynamic response, the phases switch at different frequencies and their components are selected so that the most efficient operating points correspond to the set currents. The digital controller operates on a modification of the "phase dropping" principle. Depending on the output load, the number of active phases is dynamically changed. The new architecture of the controller does not require an analog-to-digital converter for current measurement and is suitable for high-frequency low-power converters. An experimental 4-phase buck converter utilizing the digital control architecture with logarithmic current sharing was built. A comparison of the efficiency with an equivalent uniform current shared converter shows that, at medium and light loads, the presented system results in the efficiency improvements of up to 6% and 25 %, respectively.

System and Method for High Performance Image Processing

Abstract: The present invention provides a method and a system for high performance image signal processing of continuous images in real time. The system comprising a focal plane array for generating continuous source image frames in real time. The focal plane array divided logically into blocks of sub-frames. The system also comprising an analog to digital converter (ADC) layer having an array of ADC elements for converting the source image frames into a digital data. The system further comprising a digital processor layer having an array of processing elements for processing the digital data and an interconnecting layer for connecting each one of the ADC elements and the digital processing elements substantially vertically to the focal plane and substantially parallel to one another. The processing comprising reducing image motion blur, increasing image dynamic range, increasing image depth of field and obtaining features of the images.

A 10-bit 205-MS/s 1.0- $\hbox{mm}^{2}$ 90-nm CMOS Pipeline ADC for Flat Panel Display Applications

Abstract: This paper describes a 10-bit 205-MS/s pipeline analog-to-digital converter (ADC) for flat panel display applications with the techniques to alleviate the design limitations in the deep-submicron CMOS process. The switched source follower combined with a resistor-switch ladder eliminates the sampling switches and achieves high linearity for a large single-ended input signal. Multistage amplifiers adopting the complementary common-source topology increase the output swing range with lower transconductance variation and reduce the power consumption. The supply voltage for the analog blocks is provided by the low drop-out regulator for a high power-supply rejection ratio (PSRR) under the noisy operation environment. The pipeline stages of the ADC are optimized in the aspect of power consumption through the iterated calculation of the sampling capacitance and transconductance. The ADC occupies an active area of 1.0 mm2 in a 90-nm CMOS process and achieves a 53-dB PSRR for a 100-MHz noise tone with the regulator and a 55.2-dB signal-to-noise-and-distortion ratio for a 30-MHz 1.0-VPP single-ended input at 205 MS/s. The ADC core dissipates 40 mW from a 1.0-V nonregulated supply voltage.

Superconducting High-Resolution Low-Pass Analog-to-Digital Converters

Abstract: HYPRES has developed a high-resolution, dynamically programmable analog-to-digital converter (ADC) for radar and communications applications. The ADC uses the phase modulation-demodulation low-pass architecture and on-chip digital filtering. Detailed experimental results at 20 GHz clock frequency of the ADC chip fabricated with a 1 kA/cm2 Nb process are presented and discussed. In addition to the standard ADC configuration, different ADC modifications are described. In the multi-rate ADC, the modulator sampling frequency is the twice the clock frequency for the time-interleaved digital filter. In addition to the standard parallel-output ADC, a serial output ADC and its interface to room temperature electronics are developed. This serial ADC chip fabricated with the advanced HYPRES 4.5 kA/cm2 process operated up to 34 GHz clock. As a major step toward commercialization of superconducting electronics, an ADC chip was successfully packaged on a cryocooler where it showed reduced performance up to 11.52 GHz clock.

Single slope analog-to-digital converter

Abstract: A single-slope ADC, particularly suitable for use in a massive-parallel ADC architecture in a readout circuit of a CMOS imager. A plurality of ramp signals are generated which define non-overlapping sub-ranges of the full input range. For each ADC channel, the sub-range in which the voltage of the input signal falls is determined, and the corresponding ramp signal is selected for use in the A/D conversion. Thus, the speed of the A/D conversion process can be increased and the power consumption decreased.

An Ultra-Wideband 7-Bit 5 Gsps ADC Implemented in Submicron InP HBT Technology

Abstract: An ultra-wideband 7-bit 5-Gsps analog-to-digital converter (ADC), fabricated in a 4-level interconnect, 0.8 mum Indium-Phosphide (InP) heterojunction bipolar transistor (HBT) technology, is presented. This monolithic folding/interpolating ADC includes a front-end master-slave sample and hold and a pipeline stage sample and hold. The chip achieves 6 effective number of bits (ENoB) Nyquist performance at a sample rate of 5 Gsps, while dissipating 8.4 W. Furthermore, an ENoB performance of greater than 5.7 is maintained at analog input frequencies up to 7.5 GHz. This effective resolution-bandwidth product performance is significantly higher than any other previously reported monolithic ADC with sample rate ges 3 Gsps.

Method and System for Minimizing the Accumulated Offset Error for an Analog to Digital Converter

Abstract: A method and system utilized with an analog to digital converter is disclosed. The method and system comprise providing a first conversion on an input signal. In the first conversion, an offset error is added to the input signal to provide a first result. The method and system further includes providing a second conversion on the input signal. In the second conversion, an offset error is subtracted from the input signal to provide a second result. The first and second results are then combined to substantially remove the offset error. A system and method in accordance with the present invention compensates for the accumulated offset error over many samples, thereby achieving much higher accuracy in the offset error compensation.

Power management in digital receivers

Abstract: Methods and systems consistent with the present invention provide a method for dynamically controlling power consumption in a digital demodulator circuit by varying clock rates and bit widths of demodulator components including an analog to digital converter, decimation filter, OFDM operating engine, FEC decoder, and MPE-FEC processor, according to parameters and conditions of the received signal including modulation mode, signal to noise ratio, effective bit transmission rate, bit error rate, packet error rate, adjacent channel interference, and co-channel interference.

Offset Cancellation and Reduced Source Induced 1/F Noise of Voltage Reference by Using Bit Stream From Over-Sampling Analog-to-Digital Converter

Abstract: An over-sampling analog-to-digital converter (ADC) uses a chopper stabilized voltage reference with improved reference voltage offset cancellation and reduced source induced 1/f noise. The chopper stabilized voltage reference receives chopper clocks that have been correlated with the serial bitstream produced by the sigma-delta modulator of the ADC. The chopper clocks are generated so that the reference voltage produces for each distinct bitstream level an independent sequence of voltages that comprise alternatively positive and negative voltage reference offset contributions. After integration (averaging) is performed within the sigma-delta modulator, these equal and opposite reference offset contributions cancel out regardless of the bit pattern comprising the bitstream.

High-Speed Digitizing of Repetitive Waveforms Using Accurate Interleaved Sampling

Abstract: Random interleaved sampling has become a widespread operating mode for digital storage oscilloscopes. Different repetitions of (notionally) the same waveform are recorded at random time shifts and are interleaved in memory, resulting in an increase of the equivalent sampling frequency. This procedure requires substantial time, particularly if further averaging is required. In this paper, an approach that ensures accurate time shifts is presented for repeated waveform measurements. Operating two independent oscillators with related frequencies forms the accurate shifts. One of these is used to excite a waveform of interest repeatedly, and the other clocks the analog-to-digital converter (ADC). This architecture was implemented using a commercial "off-the-shelf" field programmable gate array. Examples of experimental waveforms, which are sampled at 2160 MHz using an ADC that is clocked at 80 MHz, are presented. They are compared with the simulated and independently measured waveforms where appropriate.

Cmos image sensor

Abstract: A CMOS image sensor is provided to obtain accurate linear gain distribution in a gain compensating method and make offset control of an amplifier possible by substituting an analog amplifier by a digital gain amplifier so that additional correction for a calculated control value can be possible. A CMOS image sensor comprises the followings: a variable amplifier for performing saturation level compensation of pixel data, outputted from an analog to digital converter, in a middle process; a color variable amplifier; a digital gain compensator; and a digital gain amplifier for amplifying a value, in which the saturation level compensation is performed, as much as a desired level. The digital gain amplifier comprises the followings: a digital auto exposure compensator which amplifies pixel information by using inputted pixel information and preamp gain control value and manually controls a gain rate by using an offset compensation value; and a digital auto color amplifier.

Low-Power 4-b 2.5-GSPS Pipelined Flash Analog-to-Digital Converter in 130-nm CMOS

Abstract: This paper presents a 4-b low-power, low-voltage flash analog-to-digital converter (ADC). The proposed ADC is pipelined and mainly consists of three stages: 1) track-and-hold (T/H); 2)differential comparator; and 3) differential cascode voltage switch with pass gates (DCVSPG) encoder. The T/H uses a current-mode dual-array structure to reduce the aperture jitter for high-input signal frequency. The differential comparator eliminates the use of the resistor ladder circuit by generating the reference voltages internally. The DCVSPG encoder has a full output signal swing and compact logic design style of pass gate circuits, which makes it suitable for high sampling frequency. The DCVSPG encoder reduces the power consumption by a factor of 88% as compared with the conventional ROM encoder. The ADC is designed in 130-nm CMOS technology. Fast Fourier transform tests prove proper operation of the ADC sampled at 2.5 GHz for the input signal frequency up to 1 GHz

Flexible architecture of ultra-low-power current-mode interleaved successive approximation analog-to-digital converter for wireless sensor networks

Abstract: A novel 8-bit current mode interleaved successive approximation (SAR) analog-digital converter (ADC) has been proposed. The proposed converter architecture is very flexible. Using two control DC voltages and one reference current, the converter can be tuned to work with different sampling rates, number of bits of resolution, and power consumption levels. Due to its very low-power consumption and flexibility, the converter is particularly suitable for application in wireless sensor networks. Compared to other solutions presented in the literature, the proposed converter achieves very high figure of merit (FOM) value due to numerous low-power circuit innovations utilized in its design. The circuit has been implemented in CMOS 0.18 µm technology. Minimum energy consumption has been found to be in a 25-250 kS/s range (for clock sampling frequency in a 200 kHz-2MHz range) for a single SAR section with the corresponding power dissipation varying from 220 nW to 560 nW for 0.55 V power supply.

Current mode analog-to-digital converter

Abstract: A current measuring system has an electrical component configured to provide an electrical current representative of a parameter of interest at an output node; and an analog to digital converter having a current input node in electrical communication with the output node of the electrical component.

LMS-based identification and compensation of timing mismatches in a two-channel time-interleaved analog-to-digital converter

Abstract: A time-interleaved ADC (TIADC) increases the overall sampling rate by combining multiple slow ADCs. However, the performance of a TIADC suffers from several mismatches such as time, offset, and gain mismatches. This paper deals with the identification and compensation of timing mismatches in a TIADC using the least mean square (LMS) algorithm. The method only requires a bandlimited and oversampled input signal. We present a detailed discussion and demonstrate the effectiveness of the proposed method by numerical simulations.

Hybrid delta-sigma/SAR analog to digital converter and methods for using such

Abstract: Various systems and methods for capturing data are disclosed. For example, some embodiments of the present invention provide methods for performing a first analog to digital conversion using a delta-sigma based analog to digital converter, and performing a second analog to digital conversion using a SAR based analog to digital converter. The delta-sigma converter provides a first portion of a conversion result, and the SAR based analog to digital converter provides a second portion of the conversion result. The methods further include combining the first portion of the conversion result with the second portion of the conversion result to produce a combined conversion result.

A Nanowatt Successive Approximation ADC with Offset Correction for Implantable Sensor Applications

Abstract: An 8-bit successive approximation analog-to-digital converter (ADC) with offset correction circuitry is presented for implantable sensor applications. The ADC is designed in a 0.13mum CMOS process technology and operates with voltage supplies down to 0.35 V using MOSFETs operating in their sub-threshold region of operation. Sample rates of 60kS/s are achieved with an INL and DNL of approximately 0.26LSB and 0.35LSB respectively. The SAR ADC achieves 10.7pJ/cycle operating at 20 kS/s with a 0.4 V supply. An offset correction circuit is included to dynamically minimize the offset voltage on the comparator.

Fully integrated passive UHF RFID tag with temperature sensor for environment monitoring

Abstract: A long range passive tag with temperature sensor in 0.35 mu m CMOS process has been presented. It contains five sections: RF front-end circuit, digital logical circuit, temperature sensor, a low power SAR ADC and memory circuit. The RF section contains a voltage rectifier, a voltage regulator, a PWM demodulator, a PSK backscatter modulator, and a local oscillator has been calibrated by the reader's emitting signals. The circuits of the chip work at multi supply voltage for lower power, and the total current dissipation is 15.4 mu A. A low-power 8 bit successive approximation analog to digital converter (ADC) is used to quantize the temperature output. The error of the temperature quantity output is plusmn 2degC in the range of -10 - 120degC.

Simulation of algorithms for pulse timing in FPGAs

Abstract: Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates well above 100 MHz This, combined with FPGA's low expense and ease of use, make them an ideal technology for pulse timing and are a central part of our next generation of electronics for our pre-clinical PET scanner systems To that end, our laboratory has been developing a pulse timing technique that uses pulse fitting to achieve timing resolution well below the sampling period of the analog to digital converter (ADC) While ADCs with sampling rates in excess of 400 MS/s exist, we feel that using ADCs with lowing sampling rates has many advantages for positron emission tomography (PET) scanners It is with this premise that we have started simulating timing algorithms using MATLAB in order to optimize the parameters before implementing the algorithm in Verilog MATLAB simulations allow us to quickly investigate filter designs, ADC sampling rates and algorithms with real data before implementation in hardware We report our results for a least squares fitting algorithm and a new version of a leading edge detector of PMT pulses

Calibration apparatus for mismatches of time-interleaved analog-to-digital converter

Abstract: A calibration device for calibrating an ADC comprising: an error estimator for estimating an error of a digital signal outputted from the ADC, the error estimator includes: a digital filter for filtering the digital signal to generate a filtered signal; and a least-mean-square module for performing a least-mean-square operation according to the filtered signal to generate an estimated error; and an error correction module for correcting the digital signal according to the estimated error.