Showing papers on "AND gate published in 1998"

MOS Scaling: Transistor Challenges for the 21st Century

Abstract: Conventional scaling of gate oxide thickness, source/drain extension (SDE), junction depths, and gate lengths have enabled MOS gate dimensions to be reduced from 10μm in the 1970’s to a present day size of 0.1μm. To enable transistor scaling into the 21 century, new solutions such as high dielectric constant materials for gate insulation and shallow, ultra low resistivity junctions need to be developed. In this paper, for the first time, key scaling limits are quantified for MOS transistors (see Table 1). We show that traditional SiO2 gate dielectrics will reach fundamental leakage limits, due to tunneling, for an effective electrical thickness below 2.3 nm. Experimental data and simulations are used to show that although conventional scaling of junction depths is still possible, increased resistance for junction depths below 30 nm results in performance degradation. Because of these limits, it will not be possible to further improve short channel effects. This will result in either unacceptable off-state leakage currents or strongly degraded device performance for gate lengths below 0.10μm. MOS transistor limits will be reached for 0.13μm process technologies in production during 2002. Because of these problems, new solutions will need to be developed for continued transistor scaling. We discuss some of the proposed solutions including high dielectric constant gate materials and alternate device architectures.

Programmable gate array

Abstract: An array includes a set of cells (21, 23, 25, 27, 29, 31). At least one of which includes a threshold gate (33, 35) having a plurality of inputs, an output, and a threshold value. Signals may assume an ASSERTED state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of ASSERTED inputs exceeds the threshold value. In the preferred embodiment, the gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTED inputs remains greater than zero and less than the threshold value. In an alternate embodiment, an array of simplified threshold elements is used to form more complex threshold gates.

Test generation in VLSI circuits for crosstalk noise

Abstract: This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These effects are becoming more prevalent due to short signal switching times and deep submicron circuitry. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We first present a new way for predicting the output waveform produced by an inverter due to a non-square wave pulse at its input. Our modeling technique captures such properties as the amplitude of a pulse and its rise/fall times and the delay through a device. To expedite the computation of the response of a logic gate to an input pulse, we have developed a novel way of modeling such gates by an equivalent inverter. We have developed a mixed-signal test generator that incorporates classical PODEM-like static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. We also present a new analog cost function that is used to guide the search process. Comparison of results with SPICE simulations confirms the accuracy of this approach. This paper focuses primarily on crosstalk induced pulses, but these results have been extended to deal with speedup and slowdown effects.

Cell based array comprising logic, transfer and drive cells

Abstract: A highly flexible, heterogeneous architecture for portable, high density, high performance standard cell and gate array applications is disclosed. The architecture is based on the three basic cells and their derivatives, particularly a transmission gate cell, a logic cell, and a drive cell. For gate array implementations, the cells are arranged in a pre-determined regular array format. For standard cell implementations, the arrangement of the cells may be optimized to suit each target logic gate. Optimized transistor sizing is achievable through leaf cells, software sizing, or both.

Method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology

Abstract: A method of manufacturing a memory device having embedded logic. The memory and logic FETS have two different two gate oxide 20 34 thicknesses. The method integrates (1) a salicide contact process 72 74 (logic devices) and dual gate (N+/P+) logic gate 24A 24B technology with (2) memory device Polycide with Self aligned Contact 80 Technology. The method comprises: (a) forming a first gate oxide layer 20, a first polysilicon layer 24, and a first gate cap layer 28 over said logic area 12; (b) forming memory gate structures 34 36 38 40 42A in memory area 14, (c) forming memory LDD regions 50 adjacent to said memory gate structures 24 26 28 40 in said memory area 14; (d) patterning said first gate oxide layer 20, said first polysilicon layer 24 and said first gate cap layer 28 over said logic area forming logic gate structures 20 24A & 20 24B; (e) forming spacers 66; (f) forming logic Source/drain regions 62; (g) using a salicide process to form self-aligned silicide logic S/D contacts 72 to said Source/drain regions 62, and to form self-aligned silicide logic gate contacts 74 to said logic gate structures 20 24B & 20 24A; and (h) forming self aligned polycide contacts 80 to said memory source/drain regions 50.

Cross coupled thin film transistors and static random access memory cell

Abstract: A pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first TFT and the gate of the second TFT are formed in the second polysilicon layer. A dielectric layer is interposed between the first and second polysilicon layers. The first TFT gate overlaps the second TFT drain region in the first polysilicon layer and the second TFT gate overlaps the first TFT drain region in the second polysilicon layer. In another aspect of the invention, two TFTs are incorporated into a SRAM memory cell. The memory cell includes: (i) a bit line; (ii) an access transistor having a first source/drain and a second source/drain, the first source/drain being electrically connected to the bit line; (iii) a parasitic diode formed between the second source/drain of the access transistor and the substrate; (iv) a pull down transistor having a source, drain, channel and gate; (v) a first TFT having a source, drain, channel and gate, the first TFT gate being coupled to a power supply voltage V cc through an active load device comprising a second TFT having a source, drain, channel and gate, and to a voltage not greater than ground through the pull down transistor; and (vi) a storage node for storing a high voltage representative of a first digital data state or a low voltage representative of a second digital state, the storage node being coupled to the bit line through the access transistor, to the substrate through the parasitic diode, to the pull down transistor gate and to the power supply voltage V cc through the first TFT.

All-optical AND gate based on coupled gap-soliton formation in a fiber Bragg grating.

Abstract: We experimentally demonstrate an all-optical 'AND' gate based on coupled gap soliton formation in an unchirped fibre Bragg grating. A switching contrast of better than 17dB was otained with an incident pulse peak power of 2.5kW.

Semiconductor device and manufacture thereof

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing it, where a DRAM cell and a logic circuit are enhanced in operation speed without increasing manufacturing processes in number SOLUTION: A gap between the gate electrodes 32a and 32b of MOS transistors QM as memory cells adjacent to each other is so designed as to be larger than that between the gate electrodes 32a and 32b and gate electrodes 32c and 32d which pass outside the gate electrodes 32a and 32b By this setup, an N-type diffusion layer 34a connected to a capacitor node 24 and an N-type diffusion layer 34b connected to a bit line 5 are covered with a spacer insulating film 37 A metal silicide film is formed only on the surface of the gate electrode out of the source, drain diffusion layer, and gate electrode of the first transistor of a memory cell array, and a metal silicide film is formed on the surfaces of the source, drain diffusion layer, and gate electrode of the second transistor of a logic circuit

Method for forming field effect transistor having multiple gate electrodes surrounding the channel region

Abstract: A field effect transistor comprising source and drain regions, a channel region composed of a semiconductor layer formed between the source and drain regions and gate electrodes disposed to at least three surfaces surrounding the channel region. The structure can increase the number of carriers induced in the channel region and enhance the current driving performance and mutual conductance as compared with the single gate structure or double gate structure.

Gate array semiconductor device

Abstract: In each of basic cells (BC) arranged in array in an SOI layer, PMOS and NMOS transistors are symmetrically formed. Body regions (11) and (12) are formed to divide source/drain layers (1) and (2), respectively, and gate electrodes (3) and (4) are formed on the body regions (11) and (12) respectively to sandwich gate insulating films therebetween. The gate electrodes (3) and (4) are connected at their both ends to gate contact regions (5) to (8), respectively, and the body regions (11) and (12) are connected at their one ends to body contact regions (9) and (10), respectively. The body contact regions (9) and (10) are so arranged as to sandwich the gate contact regions (5) and (7) together with the gate electrodes (3) and (4), respectively. Being of a SOI type, the device achieves high-speed operation and low power consumption. Further, with positional relation between the body contact regions (9), (10) and the gate contact regions (5), (7), the device is capable of freely setting the transistors to be of either a gate control type or a gate fixed type. As a result, the gate array type semiconductor device achieves high-speed operation and low power consumption.

Using reconfigurable computing techniques to accelerate problems in the CAD domain: a case study with Boolean satisfiability

Abstract: The Boolean satisfiability problem lies at the core of several CAD applications, including automatic test pattern generation and logic synthesis. This paper describes and evaluates an approach for accelerating Boolean satisfiability using configurable hardware. Our approach harnesses the increasing speed and capacity of field-programmable gate arrays by tailoring the SAT-solver circuit to the particular formula being solved. This input-specific technique gets high performance due both to (i) a direct mapping of Boolean operations to logic gates, and (ii) large amounts of fine grain parallelism in the implication processing. Overall, these strategies yields impressive speedups (>200/spl times/ in many cases) compared to current software approaches, and they require only modest amounts of hardware. In a broader sense, this paper alerts the hardware design community to the increasing importance of input-specific designs, and documents their promise via a quantitative study of input-specific SAT solving.

Method for dual gate oxide dual workfunction CMOS

Abstract: A method of forming integrated circuit chips including two dissimilar type NFETs and/or two dissimilar type PFETs on the same chip, such as both thick and thin gate oxide FETs. A DRAM array may be constructed of the thick oxide FETs and logic circuits may be constructed of the thin oxide FETs on the same chip. First, a gate stack including a first, thick gate SiO2 layer is formed on a wafer. The stack includes a doped polysilicon layer on the gate oxide layer, a silicide layer on the polysilicon layer and a nitride layer on the silicide layer. Part of the stack is selectively removed to re-expose the wafer where logic circuits are to be formed. A thinner gate oxide layer is formed on the re-exposed wafer. Next, gates are formed on the thinner gate oxide layer and thin oxide NFETs and PFETs are formed at the gates. After selectively siliciding thin oxide device regions, gates are etched from the stack in the thick oxide device regions. Finally, source and drain regions are implanted and diffused for the thick gate oxide devices.

Fast sequential circuit test generation using high-level and gate-level techniques

Abstract: A new approach for sequential circuit test generation is proposed that combines software based testing techniques at the high level with test enhancement techniques at the gate level. Several sequences are derived to ensure 100% coverage of all statements in a high-level VHDL description, or to maximize coverage of paths. The sequences are then enhanced at the gate level to maximize coverage of single stuck-at faults. High fault coverages have been achieved very quickly on several benchmark circuits using this approach.

FLASH-EPROM with embedded EEPROM

Abstract: Cost-efficient integration of a fully-featured EEPROM memory block in a FLASH-EPROM memory device, fabricated according to a low supply voltage and low power consumption FLASH-EPROM process, is made possible by a special structure of the EEPROM cells whereby the capacitive coupling between the floating gate and the control gate of the cell is realized over the field oxide adjacent to the active area of the cell. The process of the invention permits an optimized modulation of the thicknesses of the different tunnel and gate oxides of the FLASH-EPROM and EEPROM cells, as well as of the transistors of the peripheral circuitry of the two memory blocks destined to work with a relatively low supply voltage or with a boosted voltage.

A reconfigurable integrated circuit for high performance computer arithmetic

Abstract: In this paper, we present the design of a novel Field Programmable Gate Array (FPGA) which contains the necessary logic elements to support high performance computer arithmetic. The FPGA contains a routing framework and logic cell structure that is suitable for implementing digital systems for computer arithmetic, image processing, digital signal processing and similar computationally intensive applications. The proposed architecture is flexible, reconfigurable and will support operands of various sizes for fixed point parallel and serial binary computations.

Geometrical control of device corner threshold

Abstract: Corner conduction in a conduction channel of a field effect transistor is controlled by the geometrical configuration of the gate oxide and gate electrode at the sides of the conduction channel. Rounding the corners of the conduction channel or forming depressions at edges of trench structures such as deep or shallow trench isolation structures and/or trench capacitors develop recesses in a surface of a substrate at an interface of active areas and trench structures in which a portion of the gate oxide and gate electrode are formed so that the gate oxide and gate electrode effectively wrap around a portion of the conduction channel of the transistor. Particularly when such transistors are formed in accordance with sub-micron design rules, the geometry of the gate electrode allows the electric field in the conduction channel to be modified without angled implantation to regulate the effects of corner conduction in the conduction channel. Thus the conduction characteristic near cut-off can be tailored to specific applications and conduction/cut-off threshold voltage can be reduced at will utilizing a simple, efficient and high-yield manufacturing process.

Reduction of boron penetration by laser anneal removal of fluorine

Abstract: In one embodiment, the present invention relates to a method of removing fluorine from a gate conductor involving the steps of providing a semiconductor device containing a substrate, a gate insulator layer overlying a portion of the substrate, a gate conductor containing fluorine overlying the gate insulator layer, and a source and a drain region adjacent the gate insulator layer; and laser annealing the semiconductor device at an energy level sufficient to melt at least a portion of the gate conductor thereby inducing the removal of fluorine from the gate conductor. In another embodiment, the present invention relates to a method of making a transistor involving the steps of forming a gate conductor overlying a gate insulator layer, wherein the gate conductor and the gate insulator layer overlie a portion of a substrate, doping the substrate and gate conductor with BF 2 + to form in the substrate a source region and a drain region adjacent the gate insulator layer and a channel region between the source and drain regions and under the gate insulator layer; laser annealing the doped gate conductor, the doped source region and the doped drain region at an energy level sufficient to melt at least a portion of the doped gate conductor, thereby removing fluorine from the melted portion of the gate conductor; and subsequently performing an RTA to activate the doped source region and the doped drain region

Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry

Abstract: A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, forming from a second polysilicon layer control gate electrodes for the memory cells, and gate electrodes for the second transistors; in the first portions of the semiconductor substrate, forming source and drain regions for the first transistors; in the second portions of the semiconductor substrate, forming source and drain regions for the memory cells; in the third portions of the semiconductor substrate, forming source and drain regions for the second transistors.

Ultra-low sheet resistance metal/poly-SI gate for deep sub-micron CMOS application

Abstract: A method for fabricating a deep sub-micron gate electrode, comprising polysilicon and metal, having ultra-low sheet resistance. The process begins by forming shallow trench isolation regions 14 in a silicon substrate 10. A gate oxide layer is formed on device areas. A doped blanket polysilicon layer 16 is formed on the gate oxide layer. A cap layer 20 composed of silicon nitride is formed on the polysilicon layer 16. The cap layer 20 and the polysilicon layer 16 are patterned by photoresist masking and anisotropic etching to form a bottom gate electrode 16A and a gate cap 20A. Lightly doped source/drain areas 22 are formed adjacent to the gate bottom electrodes 16A by ion implantation. Sidewall spacers 21 are formed on the gate electrode 16A and gate cap 20A. Source/drain regions 24 are formed by ion implantation adjacent to said sidewall spacers 21. A metal silicide 23 is formed on the source/drain regions 24. An interlevel dielectric layer (ILD) 28 is deposited and planarized by CMP using the gate cap 20A as a CMP stop. The gate cap 20 is selectively removed. A barrier layer 32 composed of a TaN, CoWP, TiN or W x N y is formed over the planarized IDL 28A. A top gate layer 36 composed of copper or tungsten is formed on the barrier layer 32. The top gate layer 36 and the barrier layer 32 are removed down to the level of the top of the ILD 28 using CMP; thereby forming a top gate electrode. A passivation layer 40, composed of Pd or NiP is selectively deposited over the gate top electrode 36A.

Compound semiconductor field effect transistor

Abstract: A compound semiconductor field effect transistor having, between a gate electrode and a drain electrode, a non-gate region which is the channel region not covered by the gate electrode, wherein a plurality of isolation regions are formed in the non-gate region in such a way that they extend in the direction of channel current and contact with the gate electrode. This compound semiconductor field effect transistor is improved in breakdown voltage between drain and gate and yet retains the high-speed operability of transistor.

Multiplexing pixel circuits

Abstract: An active matrix display in accordance with the present invention includes a plurality of pixels arranged in an array. At least two transistors associated with each pixel are included. The transistors are serially connected to each other and disposed within the array for switching the pixels on and off according to data and gate signals. A data line is coupled to a first end of the serially connected transistors for each pixel. A second end of the serially connected transistors is coupled to a storage device. The serially connected transistors provide multiplexing capability for at least one of data signal multiplexing and gate signal multiplexing.

Semiconductor power converter

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor power amplifier, capable of always uniformizing the partial voltage charge of elements, even when the elements and gate drivers have variation in characteristics without reducing power conversion efficiency. SOLUTION: Delay time generating circuits T1 to Tn delay gate signal which are applied to IGBT1 to IGBTn(insulated gate bipolar transistor) and a delay time controller CNT detects allotted voltages v1 to vn, when the respective elements turn off and increases the delay times of next gate signals of the delay time generating circuits for elements other than the element having the lowest voltage on the basis of the element, thereby automatically correcting the unbalance among the voltages allotted.

Method for making field effect transistors having sub-lithographic gates with vertical side walls

Abstract: A method for the formation of field effect transistors (FETs), and more particularly metal oxide field effect transistors (MOSFETs), comprising the steps of: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a side wall layer; removing the side wall layer from horizontal surfaces of the dielectric stack and gate hole such that side wall spacers remain which reduce the lateral size of the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the semiconductor structure surrounding the gate hole; removing at least part of the dielectric stack; and removing the side wall spacers.

A threshold logic gate based on clocked coupled inverters

Abstract: In this paper we present both a new design for a threshold logic gate, based on clocked cross-coupled inverters, and the way to optimize the implementation of threshold functions using this gate. The main characteristics of the threshold gate are low power consumption (it does not consume static power) and high speed.

Loadable up-down counter with asynchronous reset

Abstract: In an FPGA having four-input lookup tables (LUTs) with parallel two-input AND gates receiving two of the four LUT input signals, associated registers, and a carry chain receiving one input signal from the AND gate output, a loadable up-down counter is formed by connecting the register output to one of the terminals serving as both a LUT input terminal and an AND gate input terminal. A load control signal is connected to another input terminal common to the LUT and the AND gate. Thus the AND gate disables the carry chain during loading of the counter and applies the count value to the carry chain during counting.

Operation of logic function in a Coulomb blockade device

Abstract: This letter presents the experimental demonstration of a Coulomb blockade (CB) logic device. Our logic architecture consists of an array of current pathways, controlled by CB switching nodes. In this architecture, high gain is not required to transmit information, making it well suited to the CB device. Each CB node is switched between a blockaded state and a completely pinched-off state, minimizing the influence of stray potentials. Using a multi-phase clocking scheme to precisely control electron flow, the AND logic function is observed using as few as 160 electrons.

A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together

Abstract: This paper presents an integrated design flow which combines floorplanning, technology mapping, and placement using a dynamic programming algorithm. The proposed design flow consists of five steps: maximum tree sub-structure formation, levelized cluster tree construction, minimum area implementation using 2-D shape functions, critical path identification, and repeated application of simultaneous floorplanning, technology mapping and gate placement along the timing critical paths. Experimental results obtained from an extensive set of benchmarks demonstrate the effectiveness of the proposed flow.

A recursive fast multiplier

Abstract: This paper presents a recursive fast multiplication algorithm. The paper defines the algorithm and applies it to two's complement signed multiplication. A step-by-step approach is given that discusses the architectural and logic implementation in detail. A random, self-checking, simulation program verifies the correctness of the recursive multiplication algorithm. The paper analyzes the speed and gate count of the design and compares the results to other multiplier designs.

Cryptographic engine using logic and base conversions

Abstract: Apparatus and method for encrypting and decrypting using permutation, concatenation and decatenation together with rotation and arithmetic and logic combining with elements or digits or characters from random, pseudo-random, or arbitrary sources wherein the plaintext may be partitioned, block-by-block, the block size being a user selectable power of 2 in size. The data bytes in the input block are selected M bytes at a time, where M≧2, with permuted addressing to form a single concatenated data byte, CDB. The CDB is modified by rotating (or barrel shifting) a random bit distance. The CDB may also be modified before or after rotation by simple arithmetic/logic operations. After modification, the CDB is broken up into M bytes and each of the M bytes is placed into the output block with permuted addressing. The output block, or ciphertext, may again be used as an input block and the process repeated with a new output block. This scheme may be used as an encryption method by itself or in conjunction other block encryption methods. The latter may be accomplished by using this scheme between successive stages of other encryption methods on blocked data, or between an internal stage of these other methods. The sources of random numbers used to determine the distance for the random rotation operation can be from: a pseudo-random number generator, sampled music CD-ROMs, entries in tables, arrays, buffers, or any other digital source.