Showing papers on "Asynchronous communication published in 1994"

Design study for a CDMA-based third-generation mobile radio system

Abstract: This paper focuses on a CDMA design study for future third-generation mobile and personal communication systems such as FPLMTS and UMTS. In the design study, a rigorous top down approach is adopted starting from the most essential objectives and requirements of universal third-generation mobile systems. Emphasis is laid on high flexibility with respect to the implementation of a wide range of services and service bit rates including variable rate and packet services. Flexibility in frequency and radio resource management, system and service deployment, and easy operation in mixed-cell and multioperator scenarios are further important design goals. The system concept under investigation is centered around an open and flexible radio interface architecture based on asynchronous direct-sequence CDMA with three different chip rates of approximately 1, 5, and 20 Mchip/s. The presented CDMA system concept forms the basis for an experimental test system (testbed) which is currently under development. This experimental system concept has been jointly established by the partners in the European RACE project R2020 (CODIT). The paper describes the radio transmission scheme and appropriate receiver principles and presents first performance results based on simulations. >

Home automation system

Abstract: A home automation system comprises a number of sub-systems for controlling various aspects of a house, such as a security sub-system, an HVAC sub-system, a lighting control sub-system, and an entertainment sub-system. The network comprises a host computer connected through a host interface to a plurality of nodes. The network is in a free form topology and employ asynchronous communication. The host computer polls each node on the network to determine system configuration and to perform a diagnostic check on the system. The messages that are transmitted between the nodes are comprised of a source address, a destination address that uniquely identifies the location of each piece of hardware on the system, a message type field, and a data length segment. Each hardware device has a mirror image software object in the host computer to which messages are directed. The user interfaces for the various sub-systems share a common interfacing method whereby use of the system is greatly simplified.

Multimedia collaboration system

Abstract: A collaboration system that integrates separate real-time and asynchronous networks - the former for real-time audio and video, and the latter for control signals and textual, graphical and other data - in a manner which closely approximates the experience of face-to-face collaboration. These capabilities are achieved by exploiting a variety of hardware, software and networking technologies in a manner that preserves the quality and integrity of audio/video/data and other multimedia information, even after wide area transmission, and at a significantly reduced networking cost as compared to what would be required by presently known approaches. The system architecture is readily scalable to the largest enterprise network environments. It accommodates differing levels of collaborative capabilities available to individual users and permits high-quality audio and video capabilities to be readily superimposed onto existing personal computers and workstations (12) and their interconnecting LANs (10) and WANs (15). In the case of a plurality of geographically dispersed LANs (10) interconnected by a WAN (15), the demands made on the WAN are significantly reduced by employing multi-hopping techniques, including avoiding the unnecessary decompression of data at intermediate hops, as well as video mosaicing and cut-and-paste technology.

Fault Tolerance in Distributed Systems

Abstract: 1. Introduction. Basic Concepts and Definitions. Phases in Fault Tolerance. Overview of Hardware Fault Tolerance. Reliability and Availability. Summary. 2. Distributed Systems. System Model. Interprocess Communication. Ordering of Events and Logical Clocks. Execution Model and System State. Summary. 3. Basic Building Blocks. Byzantine Agreement. Synchronized Clocks. Stable Storage. Fail Stop Processors. Failure Detection and Fault Diagnosis. Reliable Message Delivery. Summary. 4. Reliable, Atomic, and Causal Broadcast. Reliable Broadcast. Atomic Broadcast. Causal Broadcast. 5. Recovering A Consistent State. Asynchronous Checkpointing and Rollback. Distributed Checkpointing. Summary. 6. Atomic Actions. Atomic Actions and Serializability. Atomic Actions in a Centralized System. Commit Protocols. Atomic Actions on Decentralized Data. Summary. 7. Data Replication And Resiliency. Optimistic Approaches. Primary Site Approach. Resiliency with Active Replicas. Voting. Degree of Replication. Summary. 8. Process Resiliency. Resilient Remote Procedure Call. Resiliency with Asynchronous Communication. Resiliency with Synchronous Message Passing. Total Failure and Last Process to Fail. Summary. 9. Software Design Faults. Approaches for Uniprocess Software. Backward Recovery in Concurrent Systems. Forward Recovery in Concurrent Systems. Summary. Bibliography.

Design study for a CDMA-based third-generation mobile radio system

Abstract: This paper focuses on a CDMA design study for future third-generation mobile and personal communication systems such as FPLMTS and UMTS. In the design study, a rigorous top down approach is adopted starting from the most essential objectives and requirements of universal third-generation mobile systems. Emphasis is laid on high flexibility with respect to the implementation of a wide range of services and service bit rates including variable rate and packet services. Flexibility in frequency and radio resource management, system and service deployment, and easy operation in mixed-cell and multioperator scenarios are further important design goals. The system concept under investigation is centered around an open and flexible radio interface architecture based on asynchronous direct-sequence CDMA with three different chip rates of approximately 1,5, and 20 Mchip/s

An Asynchronous Distributed Algorithm for Power Control in Cellular Radio Systems

Abstract: We give an asynchronous adaptive algorithm for power control in cellular radio systems, which relaxes the demands of coordination and synchrony between the various mobiles and base stations. It relaxes the need for strict clock synchronization and also allows different links to update their power at different rates; unpredictable, bounded propagation delays are taken into account. The algorithm uses only local measurements and incorporates receiver noise. The overall objective is to minimize transmitters’ powers in a Pareto sense while giving each link a Carrier-to-Interference ratio which is not below a prefixed target. The condition for the existence and uniqueness of such a power distribution is obtained. Conditions are obtained for the asynchronous adaptation to converge to the optimal solution at a geometric rate. These conditions are surprisingly not burdensome.

Parallel Computing Works

Abstract: 1 Introduction 2 Technical Backdrop 3. A Methodology for Computation 4 Synchronous Applications I 5 Express and CrOS 6 Synchronous Applications II 7 Independent Parallelism 8 Full Matrix Algorithms 9 Loosely Synchronous Problems 10 DIME Programming Environment 11 Load Balancing and Optimization 12 Irregular LS Problems 13 Data Parallel C and Fortran 14 Asynchronous Applications 15 High-Level Asynchronous Software 16 The Zipcode Message-Passing System 17 MOVIE 18 Simulation and Analysis 20 Computational Science

Data transmission system and scheduling protocol for connection-oriented packet or cell switching networks

Abstract: In connection-oriented packet or cell switching networks, a data transmission system and scheduling protocol utilizes both synchronous transmission and asynchronous transmission in an alternating pattern to provide each user with both a guaranteed transmission bandwidth or capacity to accommodate real-time communications, and bandwidth sharing among users to increase network utilization, while simultaneously eliminating network congestion to avoid data losses. The synchronous time slots provide for the bandwidth guarantees, while the asynchronous time slots are used to transmit data when a part of a previous synchronous time slot is not used. The asynchronous time slots also permit asynchronous data transmission using unallocated time within a given time frame. In one embodiment, time frames for data transmission are provided in which each time frame is composed of synchronous transmission times interspersed with asynchronous transmission times. For a given time frame, alternating synchronous and asynchronous transmission times are specified by a controller which determines the pattern of this alternation. In a preferred embodiment, the pattern is altered using novel timed-round-robin scheduling which transmits cells of data of respective connections over an outgoing link depending upon the synchronous transmission time allocated to each connection. To avoid data losses, asynchronous transmission is permitted only when a downstream switch indicates sufficient buffer space to accommodate asynchronous transmission from an upstream switch.

Asynchronous secure computations with optimal resilience (extended abstract)

Abstract: We investigate the problem of multiparty computations in a fully connected, asynchronous network of n players, in which up to t Byzantine faults may occur. It was shown in [BCG93] that secure error-less multiparty computation is possible in this setting if and only if t < n/4. We show that when exponentially small probability of error is allowed, this task can be achieved even when the number of faults is in the range n/4 ~ t < n/3. From the lower bounds of [BCG93] for the asynchronous fail-stop model it follows that the resilience, t < n/3, of our protocol is optimal. We describe an ( [~1 – I)-resilient protocol that securely computes any function F. With overwhelming probability all the non-faulty players complete the execution of the protocol. Given that all the honest players terminate the protocol, they do so in time polynomial in n, in the boolean complexity of 3, and in Pog -$1, where c is the error probability. Our protocol follows the scheme of [BGW88, RB89] for multiparty computations in synchronous networks, in which the intermediary results of a circuit for F are always kept shared among the players as a verifiable secret. As the asynchronous network makes it impossible to use a regular Verifiable Secret Sharing scheme for computations, we introduce a new secret sharing scheme called Ultimate Secret Sharing. This scheme guarantees that all the honest players will obtain their share of the secret, and it enables the players to verify that the shares are genuine. “Supported by the Eshkol Fellowship of the Israel Ministry of

Fast restoration of ATM networks

Abstract: Asynchronous transfer mode (ATM) is now well recognized as the fundamental switching and multiplexing technique for future broadband ISDN. As these networks will be increasingly relied upon for providing a multitude of integrated voice, data, and video services, network reliability is a key concern. There are several intrinsic features of ATM networks that could potentially be exploited to provide improved restoration techniques, beyond those established for synchronous transfer mode (STM) networks, such as digital cross-connect restoration or self-healing rings. These features include ATM cell level error detection, inherent rate adaptation and nonhierarchical multiplexing. The authors explore the use of these features in developing fast restoration strategies for ATM networks. In particular, they address: (1) ATM error detection capabilities for enhanced failure detection, (2) network rerouting strategies, (3) spare capacity allocation, and (4) network control architecture and related implementation aspects. Their findings suggest that fast network span failure detection and bandwidth-efficient rerouting capabilities can be combined to develop restoration strategies for ATM networks with significantly greater performance-cost ratios when compared to existing STM network restoration strategies. >

Performance analysis and optimization of asynchronous circuits

Abstract: Asynchronous/self-timed circuits are beginning to attract renewed attention as a promising means of dealing with the complexity of modern VLSI designs. Very few analysis techniques or tools are available for estimating their performance. We adapt the theory of generalized timed Petri-nets (GTPN) for analyzing and comparing asynchronous circuits ranging from purely control-oriented circuits to those with data dependent control. Experiments with the GTPN analyzer are found to track the observed performance of actual asynchronous circuits, thereby offering empirical evidence towards the soundness of the modeling approach. >

The counterflow pipeline processor architecture

Abstract: The counterflow pipeline processor architecture (CFPP) is a proposal for a family of microarchitectures for RISC processors. The architecture derives its name from its fundamental feature, namely that instructions and results flow in opposite directions within a pipeline and interact as they pass. The architecture seeks geometric regularity in processor chip layout, purely local control to avoid performance limitations of complex global pipeline stall signals, and simplicity that might lead to provably correct processor designs. Moreover, CFPP designs allow asynchronous implementations, in contrast to conventional pipeline designs where the synchronization required for operand forwarding makes asynchronous designs unattractive. This paper presents the CFPP architecture and a proposal for an asynchronous implementation. Detailed performance simulations of a complete processor design are not yet available.

Asynchronous transfer mode communication with inverse multiplexing over multiple communication links

Abstract: An asynchronous transfer mode inverse multiplexed communication system is disclosed wherein a series of communication cells are multiplexed over a set of communication links. Each communication cell includes a framing bit of a predetermined framing bit stream for each communication link and a control channel bit of a control message for each communication link. Inbound communication cells from each communication link are aligned according to the corresponding framing bit stream. The control message specifies an ordered list of logical identifiers to indicate a multiplexed sequence of transfer of the communication cells over the communication links.

Integrating communication, cooperation, and awareness: the DIVA virtual office environment

Abstract: DIVA, a novel environment for group work, is presented This prototype virtual office environment provides support for communication, cooperation, and awareness in both the synchronous and asynchronous modes, smoothly integrated into a simple and intuitive interface which may be viewed as a replacement for the standard graphical user interface desktop In order to utilize the skills that people have acquired through years of shared work in real offices, DIVA is modeled after the standard office, abstracting elements of physical offices required to support collaborative work: people, rooms, desks, and documents

The timed-token protocol for real-time communications

Abstract: The timed-token protocol is a token-passing protocol in which each node receives a guaranteed share of the network bandwidth. Partly because of this property, the timed-token protocol has been incorporated into a number of network standards, including the IEEE 802.4 token bus, the Fiber Distributed Data Interface (FDDI), and the Survivable Adaptable Fiber Optic Embedded Network (Safenet). Networks based on these standards are becoming increasingly popular in new generation real-time systems. In particular, the IEEE 802.4 standard is included in the Manufacturing Automation Protocol (MAP), which has been widely used in computer-integrated manufacturing and industrial applications. Meeting message deadlines requires proper control of medium access. In the timed-token protocol, access to the communication medium is controlled by a token that is passed among the nodes in a circular fashion. Messages are segregated into two separate classes: synchronous and asynchronous. Synchronous messages, used for real-time communication, can have deadline constraints and thus are given a guaranteed share of the network bandwidth. The authors focus on meeting the deadlines of synchronous messages. >

Experimental verification of a delay compensation algorithm for integrated communication and control systems

Abstract: Advances in the technology of complex control systems demand high-speed and reliable communications between the individual components and subsystems for decision making and control. This can be accomplished by integrated communication and control systems which use asynchronous time-division-multiplexed networks. Unfortunately, these networks introduce randomly varying distributed delays as a result of time-division multiplexing. A predictor-controller algorithm has been developed with the objective of mitigating the detrimental effects of the network-induced delays that are distributed between the sensor(s), controller and actuator(s) within a control loop. This paper presents the implementation and verification of the above delay compensation algorithm. Performance of the delay compensator has been experimentally verified on an IEEE 802.4 network testbed for velocity control of a d.c. servomotor.

Asynchronous circuits for low power: a DCC error corrector

Abstract: The authors describe a complete low-power digital compact cassette error corrector. Using Tangram, a high-level programming language, they designed two asynchronous circuits that correct errors on DCC specifications. >

An FPGA for implementing asynchronous circuits

Abstract: Field-programmable gate arrays are a dominant implementation medium for digital circuits, especially for glue logic. Unfortunately, they do not support asynchronous circuits. This is a significant problem because many aspects of glue logic and communication interfaces involve asynchronous elements, or require the interconnection of synchronous components operating under independent clocks. We describe Montage, the first FPGA to explicitly support asynchronous circuit implementation, and its mapping software. Montage can be used to realize asynchronous interface circuits or to prototype complete asynchronous systems, thus bringing the benefits of rapid prototyping to asynchronous design. Unfortunately, implementation media for asynchronous circuits and systems have not kept up with those for the synchronous world. Programmable logic devices do not include the special non-digital circuits required by asynchronous design methodologies (e.g., arbiters and synchronizers) nor do they facilitate hazard-free logic implementations. This leads to huge inefficiencies in the implementation of asynchronous designs as circuits require a variety of seperate devices. This has caused most asynchronous designers to focus on custom or semi-custom integrated circuits, thus incurring greater expense in time and money. The net effect has been that optimized and robust asynchronous circuits have not become a part of typical system designs. The asynchronous circuits that must be included are usually designed in an ad-hoc manner with many underlying assumptions. This is a highly error- prone process, and causes implementations to be unnecessarily delicate to delay variations. Field-programmable gate arrays, one of today's dominant media for prototyping and implementing digital circuits, are also inappropriate for constructing more than the simplest asynchronous interfaces. They lack the critical elements at the heart of today's asynchronous designs. Unfortunately, resolving this problem is not just a simple matter of adding these elements to the programmable array. The FPGA must also have predictable routing delay and must not introduce hazards in either the logic or routing. Futhermore, the mapping tools must also be modified to handle asynchronous concerns, especially the proper decomposition of logic to fit into the programmable logic blocks and the proper routing of signals to ensure that required timing relationships are met. Ideally, we need an FPGA that can support both synchronous and asynchronous circuits with comparable efficiency. As a step in this direction we present Montage, an integrated system of FPGA architecture and mapping software designed to support both asynchronous circuits and synchronous interfaces. The architecture provides circuits with hazard-free logic and routing, mutual exclusion elements to handle metastability, and methods for initializing unclocked elements. The mapping software generates placement and signal routing sensitive to the timing demands of asynchronous methods. With these features, the Montage system forms a prototyping and implementation medium for asynchronous designs, providing asynchronous circuits with a powerful tool from the synchronous designer's toolbox.

A method of accessing a communication medium

Abstract: The invention provides for a method of accessing a communication medium that allows for isochronous and asynchronous communication traffic to share the same medium and the same transceivers of a plurality of communication stations (18,20;22,24) that communicate by way of a base station (14;16). The base station (14;16) controls the communication between the communication stations (18,20;22,24) and generates regular timing periods in which isochronous traffic (38;62,64) is sent to the stations (18,20;22,24) with a higher priority than any asynchronous traffic pending at the beginning of each timing period. Once the initial isochronous traffic (38;62,64) has accessed the medium, any further isochronous traffic retains access to the medium so that the asynchronous traffic (56,58;78) can only occur in that part of the frame period remaining after the isochronous traffic has accessed the medium.

Recording and reproducing an MPEG information signal using tagged timing information

Abstract: A method of transmitting timing critical data via an asynchronous channel without changing any datum to be transmitted. The timing critical data can be an MPEG transport stream. The asynchronous channel can be a computer or telephone network, a digital storage media such as a digital VCR, or a digital interface. The method involves tagging each transmission unit of the data stream, before inputting to the channel, with timing information, and using the timing information at the output end of the channel to recreate the proper data timing, Various schemes are described for packing the timing information tags with each or a plurality of transmission units.

Method for selecting transmission speeds for transmitting data packets over a serial bus

Abstract: In a tree topology network, a method for determining the maximum transfer speed for data packets transmitted over a high performance acyclic serial bus is disclosed The acyclic serial bus, patterned along the lines of the IEEE 1394 standard, is capable of operating at multiple transmission rates, depending upon the transmission rate of any particular node Once the transfer speeds have been determined by finding transmission rates to and from an ancestor node, an efficient storage technique for representing the transfer speeds is also disclosed The method supports packet speed selection for all types of data packets allowed by the IEEE standard, such as, for example, asynchronous, isochronous and broadcast packets

Coloured Petri Nets Extended with Channels for Synchronous Communication

Abstract: This paper shows how Coloured Petri Nets (CP-nets) can be extended to support synchronous communication. We introduce coloured communication channels through which transitions are allowed to communicate complex values. Small examples show how channel communication is convenient for creating compact and comprehensive models.

TITAC: design of a quasi-delay-insensitive microprocessor

Abstract: TITAC is an asynchronous version of an 8-bit von Neumann microprocessor based on the delay-insensitive model incorporating the isochronic-forks assumption. In its two-phase, event-driven design scheme, a working phase and an idle phase alternate to execute control and data transfer. The data path design uses a two-rail, multilevel AND-OR scheme with a binary decision diagram structure for efficient signal generation. >

A communication architecture tailored for analog VLSI artificial neural networks: intrinsic performance and limitations

Abstract: An architecture for interchip communication among analog VLSI neural networks is proposed. Activity is encoded in a neuron's pulse emission frequency. Information is transmitted through the non-arbitered, asynchronous access of pulses to a common bus. The impact of collisions when the bus is accessed by more than one user is investigated. The information-carrying capability is assessed and the trade-off between accuracy of the transmitted information and attainable dynamic range is brought out in terms of simple global parameters that characterize the application. It is found that the proposed architecture is well suited for the kind of communication requirements associated to neural computation systems. A coding scheme aimed at pushing the system towards its theoretical performance is also presented and evaluated. >

Time Stream Petri Nets: A Model for Timed Multimedia Information

Abstract: This paper introduces a model for specifying synchronization constraints in distributed asynchronous multimedia systems and applications. The consistency and semantics of multimedia systems depend on the temporal behaviour of information streams, like audio and video streams, whose synchronization constraints in asynchronous environments need to be enforced. The promoted model, named Time Stream Petri Nets (TStreamPN) allows the timed behaviour of streams to be fully, accurately and formally described using an extension of time Petri nets. This model uses time intervals to label arcs that leave the places of the net. A complete set of firing rules is also proposed to accurately enforce actual synchronization policies between different and related multimedia streams. Therefore, this model allows a formal characterization and verification of time parameters in distributed asynchronous multimedia systems.

A fully asynchronous low-power error corrector for the DCC player

Abstract: A fully asynchronous implementation of a complete DCC error corrector is presented that consumes 10 mW at 5 V, only a fifth of its synchronous counterpart, This is achieved by eliminating clocks, and exploiting the additional freedom in architecture provided by the absence of a clock. The corrector has been integrated in an experimental player and is both functionally and audibly correct. Handshake circuits are proposed as an architecture that enables structured design of asynchronous circuits through a consistent application of handshake signaling at all design levels. Handshake circuits are compiled fully automatically from high-level descriptions, and are implemented quasi delay insensitively using 4-phase handshake signaling and double-rail data encoding. The resulting circuits are self-initializable and testable. >

On the design of Chant: a talking threads package

Abstract: Lightweight threads are becoming increasingly useful for supporting parallelism and asynchronous control structures in applications and language implementations. However, lightweight thread packages for distributed memory systems have received little attention. In this paper, we introduce the design of a runtime interface, called Chant, that supports communicating threads in a distributed memory environment. In particular, Chant is layered atop standard message passing and lightweight thread libraries, and supports efficient point-to-point and remote service request communication primitives. We examine the design issues of Chant, the efficiency of its point-to-point communication layer, and the evaluation of scheduling policies to poll for the presence of incoming messages.

Pipeline synchronization

Abstract: Pipeline synchronization is a simple, low-cost, high-bandwidth, high-reliability solution to interfaces between synchronous and asynchronous systems, or between synchronous systems operating from different clocks. The technique can sustain maximum communication bandwidth while achieving an arbitrarily low, non-zero probability of synchronization failure, P/sub f/, with the price in both latency and chip area being /spl Oscr/(log 1/P/sub f/). Pipeline synchronization has been successfully applied to high-performance inter-computer communication in multicomputers and local-area networks.

The Design and Implementation of an Asynchronous Microprocessor

Abstract: A fully asynchronous implementation of the ARM microprocessor has been developed in order to demonstrate the feasibility of building complex systems using asynchronous design techniques. The design is based upon Sutherland's Micropipelines and allows considerable internal asynchronous concurrency. The design exhibits several novel features including: a register bank design which maintains coherent register operation while allowing concurrent read and write access with arbitrary timing and dependencies, the incorporation of an ALU whose speed of operation depends upon the data presented, and an instruction prefetch unit which has a non-deterministic (but bounded) prefetch depth beyond a branch. The design also includes many complex features commonly found in modern RISC processors, such as support for exact exceptions, backwards instruction set compatibility and pipelined operation. This thesis introduces the Micropipeline approach and discusses the design, organization, implementation and performance of the asynchronous ARM microprocessor which was constructed in the course of the work. No portion of the work referred to in this thesis has been submitted in support of an application for another degree of qualification of this or any other university or other institution of learning. was completed the following year. The author was then employed as a Research Assistant on the ESPRIT EDS project investigating the implementation of functional language execution mechanisms on a distributed store parallel machine. In January 1990 the author became a Research Associate working on the ESPRIT OMI-MAP project investigating the potential of asynchronous logic for low power applications. The author is currently employed as a Research Fellow working on the ESPRIT OMI-DE project which is continuing on from the work of OMI-MAP. This thesis reports the results of the work undertaken during the OMI-MAP project.

Asynchronous two-stage iterative methods

Abstract: Parallel block two-stage iterative methods for the solution of linear systems of algebraic equations are studied. Convergence is shown for monotone matrices and for H-matrices. Two different asynchronous versions of these methods are considered and their convergence investigated.