Showing papers on "Automatic test pattern generation published in 2003"

A unified approach to reduce SOC test data volume, scan power and testing time

Abstract: We present a test resource partitioning (TRP) technique that simultaneously reduces test data volume, test application time, and scan power. The proposed approach is based on the use of alternating run-length codes for test data compression. We present a formal analysis of the amount of data compression obtained using alternating run-length codes. We show that a careful mapping of the don't-cares in precomputed test sets to 1's and 0's leads to significant savings in peak and average power, without requiring either a slower scan clock or blocking logic in the scan cells. We present a rigorous analysis to show that the proposed TRP technique reduces testing time compared to a conventional scan-based scheme. We also improve upon prior work on run-length coding by showing that test sets that minimize switching activity during scan shifting can be more efficiently compressed using alternating run-length codes. Experimental results for the larger ISCAS89 benchmarks and an IBM production circuit show that reduced test data volume, test application time, and low power-scan testing can indeed be achieved in all cases.

Impact of multiple-detect test patterns on product quality

Abstract: This paper presents the impact of multiple-detect test patterns on outgoing product quality. It introduces an ATPG tool that generates multiple-detect test patterns while maximizing the coverage of node-to-node bridging defects. Volumedata obtained by testing a production ASIC with these new multiple-detect patterns shows increased defect screening capability and very good agreement with the bridging coverage estimated by the ATPG tool. 1. Introduction One of the key objectives of manufacturing test is to ensure high quality of shipped parts while managing the cost of test. Scan–based DFT methodology, combined with ATPG tools, automate the generation of test patterns with very high fault coverage. The advantage ofa structure-based ATPG tool is its high efficiency and effectiveness in generating a test set by targeting different fault models, such as stuck-at, transition, path delay, and DDQ . DFT tooI ls assess the quality of test patterns by reporting the fault coverage of the target fault models. However, real defects may not always be detected by test patterns generated for the targeted fault model. The stuck-at fault model has been used in DFT ince sthe very beginning and, while showing some limitations and imperfections, it has demonstrated its robustness and adaptability. Even though the stuck-at fault model may not always model behavior of a faulty circuit it serves very well as a target, i.e. a test set developed to test stuck-at faults will also cover many other defects that do not behave as stuck-at faults. Good understanding of bridging defects is at the center of explanation of the effectiveness of the stuck-at fault model. It also provides the key clues to its enhancements. In an experimental study of bridging faults in a state of the art microprocessor design [1] it has been observed that approximately 80% of all bridges occur between a node and Vcc or Vss, and 20% involve nonsupply nod- es. Global signals were involved in 70% of these defects and leaf-level signals contributed only 30%. In another experimental evaluation of scan tests for bridging defects [2] it was concluded that bridges with power rails contributed between 60% to 90% of all bridging defects. It is clear that a test that detect a stuck-at fault on a node willdetect a low resistive bridging defect with the supply lines. This is exactly the behavior of a node stuckat- -0 or stuckat- -1. However, the detection of node-to-node bridging defects is not guaranteed. If a stuckat fault on a node is detected once, the- probability f detecting a static bridging fault witho another un-correlated node that has signal probability 50% is also 50% [3].If the stuck at fault is detected- twice, the estimated probability of detecting the bridging fault with another node acting as an aggressor is 75%. Signal correlation may reduce the coverage of nodeto-node bridging faults. It was- observed [1] that a test set with greater than 95% stuck-at fault coverage produced only 33% coverage of nodeto-node bridging faults. Most likely the- disappointing coverage was an artifact of signal correlation. Typically a test set created by conventional ATPG aiming at single detection may have up to 6% of faults detected only once and up to 10% of faults detected only once or twice. This may result in inadequate coverage of nodeto-node -bridging defects. In general, there are two directions to overcome the limitation and improve the test quality. One direction is to enhance the fault model by describing the defect behavior and presenting it in a suitable form to the ATPG tool. In this case the fault model is more precise and complex and the fault list s longer. Thei advanced fault models, like bridging faults and cross-talk effects, use physical layout information to compile the fault lists. A complete example of this approach is demonstrated in [2]. Here the possible bridges are identified by analysis of layout using weighted critical area and their behavior is modeled by different types of faults and a special netlist. The experimental results from the project show that

High-frequency, at-speed scan testing

Abstract: The authors describe new strategies where at-speed scan tests can be applied with internal PLL. They present techniques for optimizing ATPG across multiple clock domains and methodologies to combine both stuck-at-fault and delay-test vectors into an effective test suite.

Efficient compression and application of deterministic patterns in a logic BIST architecture

Abstract: We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern generator (ATPG) and are encoded as linear feedback shift register (LFSR) initial values (seeds); one or more patterns can be encoded into a single LFSR seed. During test application, seeds are loaded into the LFSR with no cycle overhead. The method presented achieves reductions of at least 100x in test data and 10x in tester cycles compared to deterministic ATPG while maintaining complete fault coverage, as confirmed by experimental results on industrial designs.

X-tolerant compression and application of scan-atpg patterns in a bist architecture

Abstract: We present X-tolerant deterministic BIST (XDBIST), a novel method to efficiently compress and apply scan pattems generated by automatic test pattern generation (ATPG) in a logic built-in self-test architecture. Our method allows test patterns to have any number of unknown values with no degradation in compression and application efficiency. XDBIST does not require changing the core logic of the device under test (DUT); no test points or X-blockage logic need be inserted. The proposed solution guarantees the same high test coverage and diagnosis ability as deterministic scan-ATPG and uses the same tester flow, while reducing test data volume and tester cycles by more than 10 times.

An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuit

Abstract: Testing the K longest paths through each gate (KLPG) in a circuit detects the smallest local delay faults under process variation. In this work a novel automatic test pattern generation (ATPG) methodology to find the K longest testable paths through each gate in a combinational circuit is presented. Many techniques are used to significantly reduce the search space. The results on the ISCAS benchmark circuits show that this methodology is very efficient and able to handle circuits with an exponential number of paths, such as c6288.

Speed binning with path delay test in 150-nm technology

Abstract: What would it take to reduce speed binning's dependency on functional testing? One answer is a structural at-speed test approach that can achieve the same effectiveness as functional testing. The authors of this article offer a formula to relate structural critical-path testing frequency to system operation frequency. They demonstrate that there can be a high correlation between frequencies resulting from structural testing and those resulting from functional testing.

Test data compression using dictionaries with selective entries and fixed-length indices

Abstract: We present a dictionary-based test data compression approach for reducing test data volume in SOCs. The proposed method is based on the use of a small number of ATE channels to deliver compressed test patterns from the tester to the chip and to drive a large number of internal scan chains in the circuit under test. Therefore, it is especially suitable for a reduced pin-count and low-cost DFT test environment, where a narrow interface between the tester and the SOC is desirable. The dictionary-based approach not only reduces test data volume but it also eliminates the need for additional synchronization and handshaking between the SOC and the ATE. The dictionary entries are determined during the compression procedure by solving a variant of the well-known clique partitioning problem from graph theory. Experimental results for the ISCAS-89 benchmarks and representative test data from IBM show that the proposed method outperforms a number of recently-proposed test data compression techniques. Compared to the previously proposed test data compression approach based on selective Huffman coding with variable-length indices, the proposed approach generally provides higher compression for the same amount of hardware overhead.

A reconfigurable shared scan-in architecture

Abstract: In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) architecture is defined. The composite architecture is created with analysis that relies on the compatibility relation of scan chains. Topological analysis and compatibility analysis are used to maximize gains in test data volume and test application time. The goal of the proposed synthesis procedure is to test all detectable faults in broadcast test mode using minimum scan-chain configurations. As a result, more aggressive sharing of scan inputs can be applied for test data volume and test application time reduction. The experimental results demonstrate the efficiency of the proposed architecture for real-industrial circuits.

Test Data Compression Using Dictionaries with Fixed-Length Indices

Abstract: We present a dictionary-based test data compressionapproach for reducing test data volume and testing time in SOCs.The proposed method is based on the use of a small number ofATE channels to deliver compressed test patterns from the testerto the chip and to drive a large number of internal scan chainsin the circuit under test. Therefore, it is especially suitable for areduced pin-count and low-cost DFT test environment, where anarrow interface between the tester and the SOC is desirable. Thedictionary-based approach not only reduces testing time but it alsoeliminates the need for additional synchronization and handshakingbetween the SOC and the ATE. The dictionary entries are determinedduring the compression procedure by solving a variantof the well-known clique partitioning problem from graph theory.Experimental results for the ISCAS-89 benchmarks and representativetest data from IBM show that the proposed method outperformsa number of recently-proposed test data compression techniques.

Power-constrained testing of VLSI circuits

Abstract: This book is the first book that covers all asopects of power-constrained test solutions. It is a reflection of authors own research and also survey of the major contributions in this domain.

At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform

Abstract: A scan test circuitry design imbedded on an SoC having the scan architecture of a VLCT platform is disclosed herein. This BIST circuitry design that is not limited in the number of scan test ports supported includes at least one scan chain group having a corresponding clock domain that couples to receive test stimulus data. Each scan chain group has a corresponding test mode signal to shift the test stimulus data at a shift clock rate derived from its corresponding clock domain. A controlling demultiplexer connects to each multiplexer unit within each scan chain group to provide control signals for shifting in the test stimulus. A clock control mechanism provides a control signal for each scan chain to shift test stimulus and capture resultant data. Furthermore, when a simultaneous test mode signal is enabled, the clock control mechanism couples to each scan chain to enable simultaneous capture of each scan chain group.

Efficient seed utilization for reseeding based compression [logic testing]

Abstract: The conventional LFSR reseeding technique for test data compression generates one test pattern from each LFSR seed. The seed size is determined by the maximum number of specified bits in a test pattern belonging to a given test set. However, for most practical designs the majority of test patterns have significantly fewer specified bits compared to the maximum. This limits the amount of compression that can be achieved with conventional reseeding. This paper presents a new reseeding technique that overcomes this problem by generating a single test pattern from multiple seeds and multiple test patterns from a single seed. The new reseeding technique is applied to two industrial designs, resulting in significant reduction in tester memory requirement and test application time compared to the conventional reseeding technique.

Automatic multitone alternate test-generaton for rf circuits using behavioral models

Abstract: In the past, it has been diflcult to perform test generation for complex RF subsystems due to the cost of repeated system level simulation necessary for running a test generation algorithm. In this paper, a new test generation method for RF sub-systems driven by behavioral models is presented. The test generator produces an optimized multi-tone test stimulus (alternate test) from which the subsystem test specifcations can be simultaneously computed. The test generation algorithm attempts to maximize the accuracy with which all the system test spec$cations can be determined from knowledge of the different ways in which perturbations of the behavioral model parameters affect the test specifications. Pass/fil test decisions are made using the specification values computed from the observed test response (single test). Simulation results using the proposed test approach show accurate tracking of multiple system speci$ca fions, such as gain and IIP3 for the receive channel of an RF transceiver, with an error within fl dB.

Embedded deterministic test for low-cost manufacturing

Abstract: You have probably heard that BIST takes too long and its fault coverage is low, and that deterministic test requires too many patterns. This article shows how on-chip compression and decompression techniques provide high fault coverage with low test times.

On reducing test data volume and test application time for multiple scan chain designs

Abstract: We propose a new method for reducing test data volume and test application time in scan designs with multiple scan chains. The method uses a reconfigurable switch to apply tests from a limited number of external inputs to a large number of internal scan chains. The reconfigurable switch allows different subsets of scan chains to be connected to the same external input at different times, thus allowing varied tests to be applied to the circuit.

Tool-assisted unit test selection based on operational violations

Abstract: Unit testing, a common step in software development, presents a challenge. When produced manually, unit test suites are often insufficient to identify defects. The main alternative is to use one of a variety of automatic unit test generation tools: these are able to produce and execute a large number of test inputs that extensively exercise the unit under test. However, without a priori specifications, developers need to manually verify the outputs of these test executions, which is generally impractical. To reduce this cost, unit test selection techniques may be used to help select a subset of automatically generated test inputs. Then developers can verify their outputs, equip them with test oracles, and put them into the existing test suite. In this paper, we present the operational violation approach for unit test selection, a black-box approach without requiring a priori specifications. The approach dynamically generates operational abstractions from executions of the existing unit test suite. Any automatically generated tests violating the operational abstractions are identified as candidates for selection. In addition, these operational abstractions can guide test generation tools to produce better tests. To experiment with this approach, we integrated the use of Daikon (a dynamic invariant detection tool) and Jtest (a commercial Java unit testing tool). An experiment is conducted to assess this approach.

BIST-aided scan test - a new method for test cost reduction

Abstract: It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increase in test cost is caused in accordance with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIST techniques. Unfortunately, these strategies have serious constraints. We propose a new method that employs ATE and BIST structures to apply coded test patterns to LSI circuits. Results obtained using practical circuits show drastic test cost reduction capability of the proposed method.

On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits

Abstract: High-speed digital design is becoming increasingly analog. In particular, interconnect response at high frequencies can be nonmonotonic with "porch steps" and ringing. Crosstalk (both capacitive and inductive) can result in glitches on wires that can produce functional failures in receiving circuits. Most of these important effects are not addressed with traditional automatic test pattern generation (ATPG) and built-in self-test (BIST) techniques, which are limited to the binary abstraction. In this work, we explore the feasibility of integrating primitive sampling oscilloscopes on-chip to provide waveforms on selective critical nets for test and diagnosis. The oscilloscopes rely on subsampling techniques to achieve 10-ps timing accuracy. High-speed samplers are combined with delay-locked loops (DLLs) and a simple 8-bit analog-to-digital converter (ADC) to convert the waveforms into digital data that can be incorporated as part of the chip scan chain. We will describe the design and measurement of a chip we have fabricated to incorporate these oscilloscopes with a high-frequency interconnect structure in a TSMC 0.25-/spl mu/m process. The layout was extracted using Cadence's Assura RCX-PL extraction engine, enabling a comparison between simulated and measured results.

Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression

Abstract: A methodology for the determination of decompression hardware that guarantees complete fault coverage for a unified compaction/compression scheme is proposed. Test cube information is utilized for the determination of a near optimal decompression hardware. The proposed scheme attains simultaneously high compression levels and reduced pattern counts through a linear decompression hardware. Significant test volume and test application time reductions are delivered through the scheme we propose while a highly cost effective hardware implementation is retained.

Scan test method providing real time identification of failing test patterns and test controller for use therewith

Abstract: A method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern comprises performing (120) a number of test operations and storing (122) a test response signature corresponding to each block of test patterns into a signature register; replacing (124) the test response signature in the signature register with a test block expected signature; identifying (126) the block as a failing test block (128) when the test response signature is different from the test block expected signature; and repeating preceding steps until the test is complete.

Race a word-level atpg-based constraints solver system for smart random simulation

Abstract: Functional verijication of complex designs largely relies on the use of simulation in conjunction high-level verijication languages (HVL) and test-bench automation (TBA) tools. In a constraints-based verification methodology, constraints are used to model the environmental restrictions of the Design Under Verification (DUV), and are specijied using HVL constructs. The job of a constraints solver is to produce multiple random solutions to these constraints. These random solutions are used to drive legal random stimulus to the DUV using procedural HVL constructs.

Efficient sequential atpg for functional rtl circuits

Abstract: We present an efficient register-transfer level automatic test pattern generation (ATPG) algorithm. First, our ATPG generates a series of sequential justification and propagation paths for each RTL primitive via a deterministic branch-and-bound search process, called a test environment. Then the precomputed test vectors for the RTL primitives are plugged into the generated test environments to form gate-level test vectors. We augmenta 9-valuedalgebra to efficiently represent the justification and propagation objectives at the RT Level. Our ATPG automatically extracts any finite state machine (FSM) from the circuit, constructs the state transition graph (STG), and uses high-level information to guide the search process. We propose newstatic methodsto identifyembeddedcounterstructures, and we use implication-based techniques and static learning to find the FSM traversal sequences sufficient to control the counters. Finally, a simulation-based RTL extension is added to augment the deterministic test set in a few cases when there is additional room for the improvement in fault coverage. Experimental results show that our new deterministic RTL techniques achieve several orders of magnitude reduction of test generation time without compromising fault coverage when compared to gatelevel ATPG tools. Our ATPG also outperforms a recently reported simulation-based high-level ATPG tool in terms of both fault coverage and CPU time.

Test generation for designs with multiple clocks

Abstract: To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize multiple clocks in the design effectively and efficiently in order to dramatically reduce test pattern count without sacrificing fault coverage or causing clock skew problem. This is achieved by pulsing multiple noninteractive clocks simultaneously and applying a clock concatenation technique. Experimental results on several industrial circuits show significant test pattern count reduction by using the proposed test pattern generation procedures.

Analyzing the effectiveness of multiple-detect test sets

Abstract: Multiple-detect test sets have been shown to be effective in lowering defect level. Other researchers have noted that observing the effects of a defect can be controlled by sensitizing affected sites to circuit outputs but defect excitation is inherently probabilistic given a defect’s inherent, unknown nature. As a result, test sets that sensitize every signal line multiple times with varying circuit state has a greater probability of detecting a defect. In past work, the entire circuit is considered when varying circuit state from one vector to another for a given signal line. However, it may be possible to improve defect excitation by exploiting the localized nature of many defect types. Spec$cally, by varying circuit state in the physical region or neighborhood surrounding a line affected by a defect, the defect excitation and therefore detection can be improved. In this paper, we present a method for extracting a physical region surrounding a signal line but more importantly, techniques for analyzing the excitation characteristics of the region. Analysis of 4-detect test sets reveals that 30% to 60% of signal line regions do not achieve at least four unique states, indicating opportunity to further reduce defect level.

Test application time and volume compression through seed overlapping

Abstract: We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architecture of the existing SCC scheme, while it attempts to overlap consecutive test vector seeds, thus providing increased flexibility in exploiting effectively the large volume of don't-care bits in test vectors. We also introduce modified ATPG algorithms upon the previous SCC scheme and explore various implementation strategies. Experimental data exhibit significant reductions on test time and volume over all current test compression techniques.

Adjustable Width Linear Combinational Scan Vector Decompression

Abstract: A new scheme for combinational linear expansion is proposed for decompression of scan vectors. It has the capability to adjust the width of the linear expansion each clock cycle. This eliminates the requirement that every scan bit-slice be in the output space of the linear decompressor. Depending on how specified the current bit-slice is, the decompressor may load all scan chains or may load only a subset of the scan chains. This provides the nice feature that any scan vector can be generated using the proposed scheme regardless of the number or distribution of the specified bits. Thus, the proposed scheme allows the use of any ATPG procedure without any constraints. Moreover, it allows greater compression to be achieved than fixed width expansion techniques since the ratio of the number of scan chains to the number of tester channels can be scaled much larger. A procedure for designing and optimizing the adjustable width decompression hardware and obtaining the compressed data is described. Experimental data indicates that the proposed scheme is simple yet very effective.

Concurrent application of compaction and compression for test time and data volume reduction in scan designs

Abstract: A test pattern compression scheme for test data volume and application time reduction is proposed. While compression reduces test data volume, the increased number of internal scan chains due to an on-chip, fixed-rate decompressor reduces test application time proportionately. Through on-chip decompression, both the number of virtual scan chains visible to the ATE and the functionality of the ATE are retained intact. Complete fault coverage is guaranteed by constructing the decompression hardware deterministically through analysis of the test pattern set.

A circuit level fault model for resistive opens and bridges

Abstract: Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are modeled. In this paper, we propose a circuit level model for resistive open and bridge faults. All possible fault behaviors are illustrated and a general resistive bridge delay calculation method is proposed. The new models are practical and easy to use. Fault simulation results show that the new models help the delay test to catch more bridge faults.