Showing papers on "Biasing published in 1991"

Direct observation of macroscopic charge quantization

Abstract: The circuit formed by a nanoscale tunnel junction in series with a capacitance and a voltage source is the building block of most multi-junction circuits of single electronics. The state of this “single electron box” is entirely determined by the numbern of extra electrons on the intermediate “island” electrode between the junction and the capacitance. We have fabricated such a system and measured the charge on the junction capacitance, which is directly related to the average value ofn, as a function of the bias voltage using a Fulton-Dolan electrometer. At low temperature, the junction charge followed thee-periodic sawtooth function expected from the theory of macroscopic charge quantization. Strikingly,e-periodic variations were also observed when the box was superconducting. The thermal rounding of the sawtooth function is well explained by a simple model, except at the lowest temperatures.

Direct Observation of Macroscopic Charge Quantization

Abstract: The circuit formed by a nanoscale tunnel junction in series with a capacitance and a voltage source is the building block of most multi-junction circuits of single electronics. The state of this “single electron box” is entirely determined by the numbern of extra electrons on the intermediate “island” electrode between the junction and the capacitance. We have fabricated such a system and measured the charge on the junction capacitance, which is directly related to the average value ofn, as a function of the bias voltage using a Fulton-Dolan electrometer. At low temperature, the junction charge followed thee-periodic sawtooth function expected from the theory of macroscopic charge quantization. Strikingly,e-periodic variations were also observed when the box was superconducting. The thermal rounding of the sawtooth function is well explained by a simple model, except at the lowest temperatures.

Integrated charge pump circuit with back bias voltage reduction

Abstract: An integrated charge pump circuit with back bias voltage reduction includes one or more diode type voltage multiplier stages, with each stage having a diode-connected NMOS transistor in place of the conventionally-used p-n junction diode. The transistors are formed within a P-type well, which forms the back gate of each transistor within the well, and the transistor threshold voltages are dependent on the potential of the P-type well. Performance of the charge pump circuit using NMOS transistors is enhanced by the use of a bias circuit which generates a bias voltage as a function of the output voltage generated by the charge pump circuit, and applies this bias voltage to the P-type well to minimize the back-body effects of the NMOS transistors. The bias circuit thus permits the construction of an integrated charge pump circuit with significantly lower MOS diode voltage drops than would otherwise be possible.

Regulated charge pump and method therefor

Abstract: A regulated charge pump (43) includes a charge pump core (114) having a charging capacitor (80). An output voltage on a first terminal (72) of the charging capacitor (80) is transferred to a holding capacitor (81). A second terminal (73) of the charging capacitor (80) is alternatively connected to positive and negative power supply voltage terminals in response to non-overlapping clock signals. The first terminal (72) of the charging capacitor (80) is connected through first (150) and second (151) transistors to the positive power supply voltage terminal. A proportional portion (112) provides a coarse regulation by biasing the first transistor (150) proportional to a comparison between a predetermined fraction of an output voltage and a reference voltage. An integrating portion (113) provides a precise regulation by biasing the second transistor (151) proportional to an integrated difference between the output voltage and a reference voltage.

Method of and apparatus for controlling modulation of digital signals in frequency-modulated transmissions

Abstract: A signal amplitude shaping circuit (31) is interposed between a signal source (32) and a signal input terminal (16) of a frequency modulation circuit of a typical voice radio transmitter or transceiver unit. The amplitude shaping circuit (31) includes a high-impedance sampling circuit (34) which senses the steady state bias voltage at the signal input terminal during periods when no data are being transmitted. Upon receipt of a transmit-enable signal (53), the most recently sensed bias voltage is stored and positive and negative offset voltages (74, 69) are generated with respect to the stored voltage (40). One of the offset voltages (74, 69) is adjusted as a precisely determined voltage with respect to the stored voltage (40). The other of the offset voltages (69) is generated by inverting the first, adjusted voltage, such that the two offset voltages (74, 69) are offset by equal values in opposite directions. An analog switch (46) is adapted to receive a sequence of digital signals and to apply the positive and negative offset voltages (74, 69) to the signal input terminal in a sequence corresponding to the binary signal sequence of the received data signals.

Optically controlled surface‐emitting lasers

Abstract: Vertical cavity surface‐emitting lasers are integrated with GaAs/AlGaAs heterojunction phototransistors to yield optically controlled lasers. The two‐terminal device operates in several modes: As an amplifier with a large signal, external optical gain of 5, as in optical logic gate, and as an optically or electrically triggerable latch. The optical AND gate has an output on‐to‐off ratio of 10:1. Although the device has no optical feedback, latching is achieved with appropriate biasing through impact ionization. The device structure is advantageous for forming large two‐dimensional arrays for optical signal processing.

Dependence of the performance of GaAs/AlGaAs quantum well infrared photodetectors on doping and bias

Abstract: We have measured and theoretically analyzed the doping density, ND, dependence of the intersubband absorption coefficient α, the quantum efficiency η, the optical gain g, the dark current ID, and the detectivity D*. We discuss the optimum doping and show that D* depends only weakly on both ND and also the bias voltage, Vb. In particular, we find that the dark current can be reduced by three orders of magnitude, without significantly reducing the detectivity. This would substantially alleviate the undesirable filling of imaging array multiplexer storage capacitors, thereby allowing longer integration times and thus higher sensitivity.

Physical aspects of a liquid-filled ionization chamber with pulsed polarizing voltage.

Abstract: The charge collection in a liquid‐filled matrix ionization chamber system has been investigated. This system, which is used for megavoltage radiography, is scanned electronically by switching the polarizing voltage. In such a system the charge collection cannot be described by the classical ionization chamber theory since this is only valid for a fixed polarizing voltage. A model is presented for an ideal plane‐parallel ionization chamber with switched polarizing voltage that gives a good qualitative description of the physical phenomena in our nonideal system. The new model predicts the amount of charge collected and the signal‐to‐noise ratio as a function of several parameters such as electrode distance, polarizing voltage, radiation intensity, and some liquid characteristics. An important result is that the quantum noise contribution can be made quite small. This situation occurs in liquids with a low ion mobility and long ion lifetimes by a charge‐integrating effect in the liquid. Experiments were performed to test various aspects of the model. A reasonable agreement is found between theoretical and experimental results. The possible use of ultrahigh‐mobility liquids is also discussed.

Theory for photon emission from a scanning tunneling microscope

Abstract: We have calculated the rate of light emission from a scanning tunneling microscope with an Ir tip probing a silver film. In the calculation we model the tip by a sphere. We find a considerable enhancement of the light emission compared with for example inverse photoemission experiments. This enhancement is explained as the result of an amplification of the electromagnetic field in the area below the microscope tip due to a localised interface plasmon. We estimate that one out of 104 tunneling electrons will emit a photon in the visible range. Due to an electromagnetic decoupling of the sphere from the sample the enhanced emission is lost for photon energies above a certain value. We also find that the experimentally observed maximum in the light emission as a function of bias voltage is related to the behavior of tip-sample separation versus bias voltage.

Temperature dependence and post-stress recovery of hot electron degradation effects in bipolar transistors

Abstract: The authors present the results of a study of the BJT (bipolar junction transistor) degradation process due to hot electrons with the goal of better understanding the degradation rate of current gain and noise characteristics under various temperature and bias conditions. Degradation was produced by reverse biasing (-4 V) the base emitter junction of bipolar transistors at various temperatures (-75 to 240 C), with stress periods ranging from 1/60th of a second to over 1000 h. Post-stress recovery of the degradation was studied using both high-temperature annealing and base-emitter forward biases. Two mechanisms which decrease the rate of degradation at higher temperatures are the reduction in the number of hot electrons at higher temperatures and the simultaneous annealing of the states produced by hot electrons at higher temperatures. Experimental data are used to develop a model description of the hot-electron-induced gain degradation process which includes both the temperature dependence of the number of hot electrons and the temperature dependence of a simultaneous repassivation process which is observed at high ambient temperatures. >

Improved control of TiN coating properties using cathodic arc evaporation with a pulsed bias

Abstract: A combined d.c.-pulse bias voltage was used in combination with a cathodic arc evaporation process for the deposition of TiN on planar plates and drilling tools at substrate temperatures T between 330 and 500 °C. This new pulse technique appeared to be a powerful tool to achieve independent control of the substrate temperature, coating adhesion and uniformity of deposition. As a result, high coating adhesion can be obtained at low substrate temperatures. The adhesion uniformity across large-area samples is considerably improved. Unpolished rough substrate parts can be coated without cauliflower-like growth defects. Because of intensive ion bombardment in the pulse period, smoother TiN coatings with a reduced droplet size were obtained.

Control of backgate bias for low power high speed CMOS/SOI devices

Abstract: Complimentary metal oxide silicon transistors fabricated on silicon-on-insulator substrates are configured to allow separately controllable and independent backgate bias for adjacent complimentary devices on the same substrate By means of deep implantation of boron, a backgate bias P- well (26,126) is positioned on the N-substrate (17,117) at a front surface of the N- substrate behind the N channel transistor of a complimentary pair The backgate bias P- well (26,126) is provided with an electrical contact (48,148) at the front of the device, as is the N- silicon substrate to enable independent application of separate bias voltage of different polarities and appropriate magnitude

Detection of surface plasmons by scanning tunneling microscopy

Abstract: The influence of surface plasmons excited in a polycrystalline silver film on the tunneling current of a scanning tunneling microscope (STM) has been analyzed. The plasmons cause an additional flow of electrons from the tungsten tip to the silver surface on the order of up to 50 pA. This process is independent of the polarity of the applied bias voltage, thereby excluding effects of thermal expansion. The different nature of the ordinary tunneling current and the surface plasmon induced current is clearly revealed by their different dependence on the gap distance. The local distribution of the intensity of the surface plasmon induced signal reveals structures on a nanometer scale. Some of them are correlated to the surface topography.

Gated resonant tunnelling devices

Abstract: The fabrication and operation of a 1μm × 1μm gated GaAs/(AlGa)As resonant tunnelling diode is described. By biasing the gate the I/V characteristic can be varied and hence the negative differential resistance of the diode can be controlled. Using a wafer with an appropriate doping profile ensures that the maximum depletion due to the gate will occur close to the (AlGa)As tunnel barriers. When a large negative bias is applied to the gate extra structure develops in the I/V characteristic which may be related to the modification of the sub-band structure in the well due to the lateral quantum confinement of electrons by the gate. The potential of this fabrication technique is also discussed for resonant tunnelling and vertical field effect transistors.

Transport Properties of Inhomogeneous Schottky Contacts

Abstract: We review an analytical model for the interpretation of transport measurements on spatially inhomogeneous Schottky contacts. The comparison of barriers from current/voltage- as well as from capacitance/voltage-curves permits a quantitative analysis of spatially distributed Schottky barriers. We reveal that the ideality coefficient n of abrupt Schottky contacts reflects the deformation of the barrier distribution under applied bias; a general temperature dependence for the ideality n is predicted and observed. An extension of our model includes the so-called flat band barrier of current/voltage curves. Here we demonstrate the interdependence of flat band Schottky barrier, ideality n and the homogenization of the barrier distribution under the application of a bias voltage. Effective photoresponse barriers and electrical noise at inhomogeneous Schottky diodes are also discussed.

Fabry-perot modulator

Abstract: An asymetric Fabry-Perot (FP) modulator includes a quantum well structure having wider (approximately 150A) than usual (about 100A) wells. The FP cavity has a resonance at a wavelength of an excitonic absorption peak of the QW structure. Although the maximum change in absorption under applied bias is less with 150A wells than with 100A wells, the characteristics of the electroabsorption are also altered, with the result that the largest change occurs at the wavelength of the band-edge el-hhl exciton at zero bias. Absorption can be reduced by biasing the QW and hence the AFPM can have a normally-off (zero bias, zero reflectivity) characteristic. Such an arrangement makes possible higher contrast modulation and/or lower operating voltages. The FP modulator may be used in SEEDs.

Plasma-assisted cvd of carbonaceous films by using a bias voltage

Abstract: Diamond films or I-Carbon films can be formed on a surface of an object by virtue of plasma-assisted chemical vapor deposition. The hardness of the films can be enhanced by applying a bias voltage to the object during deposition.

Wireless intercom having a transceiver in which a bias current for the condenser microphone and the driving current for the speaker are used to charge a battery during transmission and reception, respectively

Abstract: In a voice-controllable transceiver of a wireless intercom, the bias voltage for the condenser microphone is divided during transmission to give a current of 0.6 mA to 1mA. During reception, the driving voltage for the speaker is multiplied and rectified to a current of 1mA to 30mA. Both currents are used to charge a battery, resulting in a voice-controllable circuit having low power consumption circuit. The voice-controllable transceiver therefore does not require an external power source or frequent battery replacement.

Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts

Abstract: A method for maintaining optimum biasing voltage and standby current levels in a dynamic random access memory array, in which row-to-column shorts have been repaired by redirecting the addresses of shorted rows and columns to spare rows and columns. The method partly consists of placing a current limiting device in series with the bias voltage generator output and the nodes between the equilibration transistors of small groups of digit line pairs. The current limiting devices may be either long-L transistors that are in an always-on state, or they may be merely resistive elements, such as strips of lightly-doped polysilicon. The invention effectively isolates the effect of row-to-column shorts in a portion of a DRAM array from the remainder of the array. All digit line pairs tied to a single current limiting device are replaced as a unit if any one or more of the digit lines among the tied pairs is shorted to a word line. The method further consists of holding the common node of each P-type sense amplifiers at no more than a threshold voltage above ground potential during digit line equilibration, rather than at half of power supply voltage, in order to eliminate an unwanted current path from an off-chip power supply, through sundry intervening circuitry, to the common node of a P-type sense amplifier, through the transistors of the P-type sense amplifier, to a bitline which is shorted to one of the rowlines, which are normally held at ground potential during the same period.

A new MOS imager using photodiode as current source

Abstract: The author presents a MOS linear image sensor having a high-voltage gain amplifier in photodiode pixels. The only difference between the amplified MOS image (AMI) and this new device is the transfer gate added between the photodiode pixel and the source follower. In this structure, the photoinduced charge loss in video-line parasitic capacitance is compensated to improve the sensitivity. A high-voltage-gain amplifier is used to control the input voltage of the transfer gate so as to maintain an unchanged bias voltage of the photodiode and by operating the photodiode cell as a current source. In this device, the photoinduced charge is not divided by the photodiode capacitance C/sub d/ or the capacitive load C/sub t/. Therefore, it is possible to enlarge the photodiode size, and the sensor has a large saturation exposure as well as a large photocurrent/dark-current ratio of about 30:1. The device operates on a single 5 V power supply. These features make the device suitable for applications in low light levels. >

Laser diode driving circuit

Abstract: PURPOSE:To compensate the fluctuation of an extinct ratio of a laser diode by using a current source circuit employing a diode having a same temperature characteristic as that of the laser diode and varying a signal amplitude current with the current source circuit. CONSTITUTION:A bias voltage depending on a forward voltage of a diode D and a constant current i1 generated by a constant current source 1 is applied to the base of a transistor(TR) Q3. The forward voltage is decreased in the diode D as the temperature rises. Thus, the voltage applied to the base of the TR Q3 is boosted to increase a modulation current i2 applied to the laser diode LD. As soon as a differentiation efficiency of the laser diode LD is changed, the voltage drop of the diode D is decreased, the voltage applied to the base of the TR Q3 is boosted and the modulation current i2 applied to the laser diode LD is increased. Thus, the signal amplitude of an outputted optical signal is unchanged regardless of the fluctuation in the differentiation efficiency of the laser diode LD.

Electrical characteristics of Si3N4/Si/GaAs metal‐insulator‐semiconductor capacitor

Abstract: We report on the electrical characteristics of an as‐grown Si3N4/Si/n‐GaAs metal‐insulator‐semiconductor capacitors. The GaAs layer is grown by molecular beam epitaxy and both the Si3N4 and the 10 A Si layers are deposited using silane in a vacuum connected ultrahigh vacuum chemical vapor deposition chamber driven by an electron cyclotron resonance plasma source. The current‐voltage characteristics of the Si3N4 films at high fields can be best represented by Fowler–Nordheim tunneling indicative of the high quality of the films. Hole inversion of the n‐GaAs layer is clearly seen in the quasi‐static capacitance‐voltage curve. Despite past reports on the presence of a large amount of bulk traps in Si3N4, a hysteresis of less than 100 meV is observed in the high‐frequency capacitance‐voltage curves with a bias voltage swing of ±4 V. From the high‐low capacitance method we estimated the interface trap density to be of the order of 4×1011 eV−1 cm−2 and from the conductance measurements we found a value of 1012 ...

Magnetic recording channel front-ends

Abstract: Readback front-end electronics for both inductive and magnetic recording (MR) heads are investigated. For inductive front-ends, it is shown that the channel bandwidth is determined by the transfer of the induced head voltage to the front-end input terminals. The parameters limiting this bandwidth are calculated. A noise analysis shows that the signal-to-noise ratio can be optimized and gives the parameter values for which this happens. The effect of noise matching of the head to the front-end is demonstrated. For MR front-ends the principles of auto bias and relative resistance sensing are presented. Front-end configurations producing voltage biasing and current biasing are discussed. Two examples of signal conditioning in MR front-ends are given: an on-the-chip equalizer compensating the frequency roll-off introduced by the head cable inductance, and a signal-adaptive circuit for removing thermal asperities. >

Optoelectronic properties of hydrogenated amorphous silicon films deposited under negative substrate bias

Abstract: We present a detailed study of the effects of ion bombardment on the optoelectronic properties of a‐Si:H films. Two series of samples were deposited from a rf glow discharge at 30 and 100 mTorr of silane pressure, corresponding to two different deposition conditions. The energy of the ions impinging on the substrate was increased by applying a negative dc bias in steps of 25 V to the substrate holder. The increase of the substrate bias from 0 to −100 V had no effect on the deposition rate of a‐Si:H at 30 mTorr, whereas a factor of 2 decrease was observed for deposition at 100 mTorr. The density of states of the a‐Si:H films, determined by photothermal deflection spectroscopy and by the constant‐photocurrent method, decreased as the substrate bias was increased up to −50 V, especially for the series deposited at 100 mTorr. At the same time the valence‐band tail became sharper. These observations are consistent with the improvement of the electron drift‐mobility deep‐trapping‐lifetime (μdτd)e product, deter...

Trim correction circuit with temperature coefficient compensation

Abstract: An op amp bias system that provides input offset voltage trim current with minimum offset thermal drift The bias system includes a bias generator that provides bias current to the op amp and correction circuitry responsive to the bias current for providing an input offset trim current that compensates for offset drift error with changes in temperature

Analysis of r.f.-sputtered TiB2 hard coatings by means of X-ray diffractometry and Auger electron spectroscopy

Abstract: The bias voltage can be a very important parameter in r.f. sputtering. Auger electron spectroscopy (AES) and X-ray diffraction (XRD) were used to investigate the influence of this parameter on TiB 2 hard coatings. As a result of the AES measurements the boron-to-titanium ratio depends on the bias voltage. With XRD, significant differences in the various coatings can be observed.

Static random access memory including stress test circuitry

Abstract: SRAM comprises a word line driving circuit selecting a predetermined number of word lines in accordance with an input address at the time of a normal operation, and simultaneously selecting all word lines or word lines, which are more than the number of word lines to be selected at the time of the normal operation, at the time of a voltage stress applying test, and a bit line load circuit applying a predetermined bias voltage to said pair of bit lines at the time of the normal operation, and controlling the bias voltage not to be applied to at least one of said pair of bit lines or applying the bias voltage, which is lower than the bias voltage at the time of the normal operation, at the time of the voltage stress test.

Low-power demodulating receiver with amplifier stages sharing the same bias current

Abstract: A low-power receiver for extracting a digital data signal from a modulated carrier signal is disclosed. The receiver employs an amplifier whose stages share the same bias current in order to reduce power consumption.

A CMOS off chip driver for fault tolerant cold sparing

Abstract: A full swing CMOS logic circuit provides fault tolerant, cold sparing of VLSI logic devices attached to a high speed bus. P-channel FET transistors are formed in an N-well which has a biasing transistor which effectively decouples the circuit when the circuit is not powered. The input/output interface of the cold spares have a high impedance and do not corrupt an interconnected electronic bus. The final drive transistors are reverse biased or clamped to zero to prevent any leakage paths.